Lines Matching +refs:tablegen +refs:mode +refs:map

1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
1385 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1508 // pseudos map between the two.
1528 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1611 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
2043 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
3693   bits<5> mode;
3700   let Inst{4-0}   = mode;
3705   def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3706                       "$imod\t$iflags, $mode">;
3707 let mode = 0, M = 0 in
3711   def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3713 def : t2InstAlias<"cps$imod.w $iflags, $mode",
3714                    (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>;
3715 def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
3782   bits<5> mode;
3789   let Inst{4-0} = mode{4-0};
3793 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3794                         "srsdb", "\tsp!, $mode", []>;
3795 def t2SRSDB  : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3796                      "srsdb","\tsp, $mode", []>;
3797 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3798                         "srsia","\tsp!, $mode", []>;
3799 def t2SRSIA  : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3800                      "srsia","\tsp, $mode", []>;
3803 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3804 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3806 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3807 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3862 // ERET - Return from exception in Hypervisor mode.