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Lines Matching refs:isLd

1379   bool isLd = isLoadSingle(Opcode);  in MergeBaseUpdateLoadStore()  local
1388 .addReg(Base, getKillRegState(isLd ? BaseKill : false)) in MergeBaseUpdateLoadStore()
1390 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
1392 } else if (isLd) { in MergeBaseUpdateLoadStore()
1598 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8; in FixInvalidRegPairOp() local
1599 bool EvenDeadKill = isLd ? in FixInvalidRegPairOp()
1602 bool OddDeadKill = isLd ? in FixInvalidRegPairOp()
1616 unsigned NewOpc = (isLd) in FixInvalidRegPairOp()
1619 if (isLd) { in FixInvalidRegPairOp()
1623 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1624 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
1638 unsigned NewOpc = (isLd) in FixInvalidRegPairOp()
1643 unsigned NewOpc2 = (isLd) in FixInvalidRegPairOp()
1649 if (isLd && in FixInvalidRegPairOp()
1653 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2, in FixInvalidRegPairOp()
1657 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, in FixInvalidRegPairOp()
1672 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, in FixInvalidRegPairOp()
1676 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2, in FixInvalidRegPairOp()
1681 if (isLd) in FixInvalidRegPairOp()
1980 unsigned Base, bool isLd,
2008 static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base, in IsSafeAndProfitableToMove() argument
2023 if (isLd && I->mayStore()) in IsSafeAndProfitableToMove()
2025 if (!isLd) { in IsSafeAndProfitableToMove()
2131 unsigned Base, bool isLd, in RescheduleOps() argument
2201 DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp, in RescheduleOps()
2208 MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp; in RescheduleOps()
2236 if (isLd) { in RescheduleOps()
2322 bool isLd = isLoadSingle(Opc); in RescheduleLoadStoreInstrs() local
2327 if (isLd) { in RescheduleLoadStoreInstrs()