98     bool isThumb1, isThumb2;  member
461   assert(isThumb1 && "Can only update base register uses for Thumb1!");  in UpdateBaseRegUses()
603   bool SafeToClobberCPSR = !isThumb1 ||  in CreateLoadStoreMulti()
607   bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback.  in CreateLoadStoreMulti()
612   if (isThumb1 && isi32Load(Opcode) && ContainsReg(Regs, Base)) {  in CreateLoadStoreMulti()
624   bool haveIBAndDA = isNotVFP && !isThumb2 && !isThumb1;  in CreateLoadStoreMulti()
630   } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) {  in CreateLoadStoreMulti()
664       NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass);  in CreateLoadStoreMulti()
671       (isThumb1 && Base == ARM::SP) ? ARM::tADDrSPi :  in CreateLoadStoreMulti()
672       (isThumb1 && Offset < 8) ? ARM::tADDi3 :  in CreateLoadStoreMulti()
673       isThumb1 ? ARM::tADDi8  : ARM::ADDri;  in CreateLoadStoreMulti()
679         (isThumb1 && Offset < 8 && Base != ARM::SP) ? ARM::tSUBi3 :  in CreateLoadStoreMulti()
680         isThumb1 ? ARM::tSUBi8  : ARM::SUBri;  in CreateLoadStoreMulti()
692     if (isThumb1) {  in CreateLoadStoreMulti()
752   if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)  in CreateLoadStoreMulti()
758     assert(isThumb1 && "expected Writeback only inThumb1");  in CreateLoadStoreMulti()
1206   if (isThumb1) return false;  in MergeBaseUpdateLSMultiple()
1333   if (isThumb1) return false;  in MergeBaseUpdateLoadStore()
1855   if (isThumb1) return false;  in MergeReturnIntoLDM()
1925   isThumb1 = AFI->isThumbFunction() && !isThumb2;  in runOnMachineFunction()
1934     if (isThumb1)  in runOnMachineFunction()