314 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const {  in getRegBitWidth()
324   if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) {  in getRegBitWidth()
325     const TargetRegisterClass *VC = MRI.getRegClass(RR.Reg);  in getRegBitWidth()
329     assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg));  in getRegBitWidth()
330     PhysR = RR.Reg;  in getRegBitWidth()
333   unsigned PhysS = (RR.Sub == 0) ? PhysR : TRI.getSubReg(PhysR, RR.Sub);  in getRegBitWidth()
340 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR,  in getCell()  argument
342   uint16_t BW = getRegBitWidth(RR);  in getCell()
346   if (TargetRegisterInfo::isPhysicalRegister(RR.Reg))  in getCell()
349   assert(TargetRegisterInfo::isVirtualRegister(RR.Reg));  in getCell()
352   const TargetRegisterClass *C = MRI.getRegClass(RR.Reg);  in getCell()
356   CellMapType::const_iterator F = M.find(RR.Reg);  in getCell()
358     if (!RR.Sub)  in getCell()
360     BitMask M = mask(RR.Reg, RR.Sub);  in getCell()
368 void BT::MachineEvaluator::putCell(const RegisterRef &RR, RegisterCell RC,  in putCell()  argument
373   if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))  in putCell()
375   assert(RR.Sub == 0 && "Unexpected sub-register in definition");  in putCell()
380       RC[i].RefI = BitRef(RR.Reg, i);  in putCell()
382   M[RR.Reg] = RC;  in putCell()
995 BT::RegisterCell BT::get(RegisterRef RR) const {  in get()
996   return ME.getCell(RR, Map);  in get()
1000 void BT::put(RegisterRef RR, const RegisterCell &RC) {  in put()  argument
1001   ME.putCell(RR, RC, Map);  in put()