Lines Matching refs:BitTracker
159 static bool isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1,
160 const BitTracker::RegisterCell &RC2, uint16_t B2, uint16_t W);
161 static bool isZero(const BitTracker::RegisterCell &RC, uint16_t B,
163 static bool getConst(const BitTracker::RegisterCell &RC, uint16_t B,
167 static bool getSubregMask(const BitTracker::RegisterRef &RR,
174 BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH);
182 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI);
183 static bool isTransparentCopy(const BitTracker::RegisterRef &RD,
184 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI);
268 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, in isEqual()
269 uint16_t B1, const BitTracker::RegisterCell &RC2, uint16_t B2, in isEqual()
273 if (RC1[B1+i].Type == BitTracker::BitValue::Ref && RC1[B1+i].RefI.Reg == 0) in isEqual()
276 if (RC2[B2+i].Type == BitTracker::BitValue::Ref && RC2[B2+i].RefI.Reg == 0) in isEqual()
284 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, in isZero()
294 bool HexagonBitSimplify::getConst(const BitTracker::RegisterCell &RC, in getConst()
299 const BitTracker::BitValue &BV = RC[i-1]; in getConst()
363 bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR, in getSubregMask()
390 BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH) { in parseRegSequence()
850 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) { in getFinalVRegClass()
880 bool HexagonBitSimplify::isTransparentCopy(const BitTracker::RegisterRef &RD, in isTransparentCopy()
881 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI) { in isTransparentCopy()
1001 RedundantInstrElimination(BitTracker &bt, const HexagonInstrInfo &hii, in RedundantInstrElimination()
1013 bool usedBitsEqual(BitTracker::RegisterRef RD, BitTracker::RegisterRef RS);
1017 BitTracker &BT;
1161 BitTracker::RegisterRef UR = *I; in computeUsedBits()
1207 BitTracker::RegisterRef RR = MI.getOperand(OpN); in computeUsedBits()
1225 bool RedundantInstrElimination::usedBitsEqual(BitTracker::RegisterRef RD, in usedBitsEqual()
1226 BitTracker::RegisterRef RS) { in usedBitsEqual()
1227 const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg); in usedBitsEqual()
1228 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in usedBitsEqual()
1266 BitTracker::RegisterRef RD = MI->getOperand(0); in processBlock()
1269 const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg); in processBlock()
1277 BitTracker::RegisterRef RS = Op; in processBlock()
1287 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in processBlock()
1298 BT.put(BitTracker::RegisterRef(NewR), SC); in processBlock()
1316 ConstGeneration(BitTracker &bt, const HexagonInstrInfo &hii, in ConstGeneration()
1328 BitTracker &BT;
1335 const BitTracker::RegisterCell &RC = BT.lookup(R); in isConst()
1338 const BitTracker::BitValue &V = RC[i-1]; in isConst()
1459 CopyGeneration(BitTracker &bt, const HexagonInstrInfo &hii, in CopyGeneration()
1464 bool findMatch(const BitTracker::RegisterRef &Inp,
1465 BitTracker::RegisterRef &Out, const RegisterSet &AVs);
1469 BitTracker &BT;
1489 bool CopyGeneration::findMatch(const BitTracker::RegisterRef &Inp, in findMatch()
1490 BitTracker::RegisterRef &Out, const RegisterSet &AVs) { in findMatch()
1493 const BitTracker::RegisterCell &InpRC = BT.lookup(Inp.Reg); in findMatch()
1501 const BitTracker::RegisterCell &RC = BT.lookup(R); in findMatch()
1550 BitTracker::RegisterRef MR; in processBlock()
1559 BT.put(BitTracker::RegisterRef(NewR), BT.get(MR)); in processBlock()
1587 BitTracker::RegisterRef RD = MI.getOperand(0); in propagateRegCopy()
1594 BitTracker::RegisterRef RS = MI.getOperand(1); in propagateRegCopy()
1604 BitTracker::RegisterRef SL, SH; in propagateRegCopy()
1614 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); in propagateRegCopy()
1626 BitTracker::RegisterRef RS = MI.getOperand(SrcX); in propagateRegCopy()
1661 BitSimplification(BitTracker &bt, const HexagonInstrInfo &hii, in BitSimplification()
1666 struct RegHalf : public BitTracker::RegisterRef {
1670 bool matchHalf(unsigned SelfR, const BitTracker::RegisterCell &RC,
1673 bool matchPackhl(unsigned SelfR, const BitTracker::RegisterCell &RC,
1674 BitTracker::RegisterRef &Rs, BitTracker::RegisterRef &Rt);
1679 bool genPackhl(MachineInstr *MI, BitTracker::RegisterRef RD,
1680 const BitTracker::RegisterCell &RC);
1681 bool genExtractHalf(MachineInstr *MI, BitTracker::RegisterRef RD,
1682 const BitTracker::RegisterCell &RC);
1683 bool genCombineHalf(MachineInstr *MI, BitTracker::RegisterRef RD,
1684 const BitTracker::RegisterCell &RC);
1685 bool genExtractLow(MachineInstr *MI, BitTracker::RegisterRef RD,
1686 const BitTracker::RegisterCell &RC);
1687 bool simplifyTstbit(MachineInstr *MI, BitTracker::RegisterRef RD,
1688 const BitTracker::RegisterCell &RC);
1692 BitTracker &BT;
1701 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf()
1729 const BitTracker::RegisterCell &SC = BT.lookup(Reg); in matchHalf()
1734 const BitTracker::BitValue &RV = RC[i+B]; in matchHalf()
1735 if (RV.Type == BitTracker::BitValue::Ref) { in matchHalf()
1782 const BitTracker::RegisterCell &RC, BitTracker::RegisterRef &Rs, in matchPackhl()
1783 BitTracker::RegisterRef &Rt) { in matchPackhl()
1820 BitTracker::RegisterRef RS = ValOp; in genStoreUpperHalf()
1823 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreUpperHalf()
1864 BitTracker::RegisterRef RS = MI->getOperand(2); in genStoreImmediate()
1867 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreImmediate()
1910 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genPackhl()
1914 BitTracker::RegisterRef Rs, Rt; in genPackhl()
1927 BT.put(BitTracker::RegisterRef(NewR), RC); in genPackhl()
1935 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genExtractHalf()
1963 BT.put(BitTracker::RegisterRef(NewR), RC); in genExtractHalf()
1971 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genCombineHalf()
1994 BT.put(BitTracker::RegisterRef(NewR), RC); in genCombineHalf()
2002 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genExtractLow()
2033 BitTracker::RegisterRef RS = Op; in genExtractLow()
2036 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in genExtractLow()
2053 BT.put(BitTracker::RegisterRef(NewR), RC); in genExtractLow()
2067 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in simplifyTstbit()
2073 BitTracker::RegisterRef RS = MI->getOperand(1); in simplifyTstbit()
2082 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in simplifyTstbit()
2083 const BitTracker::BitValue &V = SC[F+BN]; in simplifyTstbit()
2084 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg != RS.Reg) { in simplifyTstbit()
2090 BitTracker::RegisterRef RR(V.RefI.Reg, 0); in simplifyTstbit()
2149 BitTracker::RegisterRef RD = Op0; in processBlock()
2153 const BitTracker::RegisterCell &RC = BT.lookup(RD.Reg); in processBlock()
2194 BitTracker BT(HE, MF); in runOnMachineFunction()
2317 BitTracker *BTP;
2326 BitTracker::RegisterRef Inp, Out;
2332 BitTracker::RegisterRef LR, PR;
2384 const BitTracker::RegisterCell &RC = BTP->lookup(Reg); in isConst()
2386 const BitTracker::BitValue &V = RC[i]; in isConst()
2441 const BitTracker::RegisterCell &OutC = BTP->lookup(OutR); in isShuffleOf()
2443 const BitTracker::BitValue &V = OutC[i]; in isShuffleOf()
2444 if (V.Type != BitTracker::BitValue::Ref) in isShuffleOf()
2457 const BitTracker::RegisterCell &OutC1 = BTP->lookup(OutR1); in isSameShuffle()
2458 const BitTracker::RegisterCell &OutC2 = BTP->lookup(OutR2); in isSameShuffle()
2464 const BitTracker::BitValue &V1 = OutC1[i], &V2 = OutC2[i]; in isSameShuffle()
2465 if (V1.Type != V2.Type || V1.Type == BitTracker::BitValue::One) in isSameShuffle()
2467 if (V1.Type != BitTracker::BitValue::Ref) in isSameShuffle()
2733 BitTracker BT(HE, MF); in runOnMachineFunction()