Lines Matching refs:NewR
165 static bool replaceReg(unsigned OldR, unsigned NewR,
169 static bool replaceRegWithSub(unsigned OldR, unsigned NewR,
172 unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI);
311 bool HexagonBitSimplify::replaceReg(unsigned OldR, unsigned NewR, in replaceReg() argument
314 !TargetRegisterInfo::isVirtualRegister(NewR)) in replaceReg()
320 I->setReg(NewR); in replaceReg()
326 bool HexagonBitSimplify::replaceRegWithSub(unsigned OldR, unsigned NewR, in replaceRegWithSub() argument
329 !TargetRegisterInfo::isVirtualRegister(NewR)) in replaceRegWithSub()
335 I->setReg(NewR); in replaceRegWithSub()
343 unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI) { in replaceSubWithSub() argument
345 !TargetRegisterInfo::isVirtualRegister(NewR)) in replaceSubWithSub()
353 I->setReg(NewR); in replaceSubWithSub()
1294 unsigned NewR = MRI.createVirtualRegister(FRC); in processBlock() local
1295 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR) in processBlock()
1297 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in processBlock()
1298 BT.put(BitTracker::RegisterRef(NewR), SC); in processBlock()
1555 unsigned NewR = MRI.createVirtualRegister(FRC); in processBlock() local
1557 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR) in processBlock()
1559 BT.put(BitTracker::RegisterRef(NewR), BT.get(MR)); in processBlock()
1919 unsigned NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass); in genPackhl() local
1923 BuildMI(B, At, DL, HII.get(Hexagon::S2_packhl), NewR) in genPackhl()
1926 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genPackhl()
1927 BT.put(BitTracker::RegisterRef(NewR), RC); in genPackhl()
1947 unsigned NewR = 0; in genExtractHalf() local
1951 NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genExtractHalf()
1952 BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR) in genExtractHalf()
1955 NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genExtractHalf()
1956 BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR) in genExtractHalf()
1960 if (NewR == 0) in genExtractHalf()
1962 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genExtractHalf()
1963 BT.put(BitTracker::RegisterRef(NewR), RC); in genExtractHalf()
1987 unsigned NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genCombineHalf() local
1990 BuildMI(B, At, DL, HII.get(COpc), NewR) in genCombineHalf()
1993 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genCombineHalf()
1994 BT.put(BitTracker::RegisterRef(NewR), RC); in genCombineHalf()
2043 unsigned NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genExtractLow() local
2046 auto MIB = BuildMI(B, At, DL, HII.get(NewOpc), NewR) in genExtractLow()
2052 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genExtractLow()
2053 BT.put(BitTracker::RegisterRef(NewR), RC); in genExtractLow()
2102 unsigned NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in simplifyTstbit() local
2103 BuildMI(B, At, DL, HII.get(Hexagon::S2_tstbit_i), NewR) in simplifyTstbit()
2106 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyTstbit()
2107 BT.put(NewR, RC); in simplifyTstbit()
2111 unsigned NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in simplifyTstbit() local
2113 BuildMI(B, At, DL, HII.get(NewOpc), NewR); in simplifyTstbit()
2114 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyTstbit()