Lines Matching refs:IntRegs
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
70 (ins IntRegs:$src1, ImmOp:$src2),
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
98 (MI IntRegs:$src1, ImmPred:$src2)>;
121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
229 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
230 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
257 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
289 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
290 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
300 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
301 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
320 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
321 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
351 : ALU32_ri <(outs IntRegs:$Rd),
352 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
377 : ALU32_ri <(outs IntRegs:$Rd),
378 (ins IntRegs:$Rs, immOp:$s16),
423 : ALU32_ri <(outs IntRegs:$Rd),
435 : ALU32_ri <(outs IntRegs:$Rd),
436 (ins IntRegs:$Rs, s10Ext:$s10),
438 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> {
461 def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
483 def: Pat<(sub s32ImmPred:$s10, IntRegs:$Rs),
484 (A2_subri imm:$s10, IntRegs:$Rs)>;
487 def: Pat<(not (i32 IntRegs:$src1)),
488 (A2_subri -1, IntRegs:$src1)>;
492 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
513 : ALU32Inst<(outs IntRegs:$dst),
514 (ins PredRegs:$src1, IntRegs:$src2),
536 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
601 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
630 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
631 [(set (i32 IntRegs:$Rd), s32ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
675 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
692 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
696 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
708 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
711 [(set (i32 IntRegs:$Rd),
740 ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
761 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
815 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
1019 (outs PredRegs:$Pd), (ins IntRegs:$Rs, s8Ext:$s8),
1022 (outs PredRegs:$Pd), (ins IntRegs:$Rs, u8Ext:$s8),
1047 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1130 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1146 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1188 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1194 (Inst IntRegs:$src1, IntRegs:$src2)>;
1200 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1396 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1506 : JRInst<(outs), (ins IntRegs:$dst),
1518 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1556 dag InputDag = (ins IntRegs:$Rs)>
1578 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1579 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1624 def: Pat<(brind (i32 IntRegs:$dst)),
1625 (J2_jumpr IntRegs:$dst)>;
1639 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1672 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1728 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1729 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1733 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1734 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1738 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1744 def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>;
1745 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
1757 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1790 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1791 (VT (MI IntRegs:$Rs, imm:$Off))>;
1792 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1818 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1819 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1830 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1831 (ins IntRegs:$src1, ImmOp:$offset),
1864 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1865 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1922 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1923 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1928 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1929 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1934 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1943 def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
1944 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
1956 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2),
1957 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1992 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1993 (ins IntRegs:$src1, ModRegs:$src2),
2013 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
2014 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
2015 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
2016 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
2017 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
2019 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
2029 (ins IntRegs:$addr, s11_2Ext:$off),
2035 (ins IntRegs:$addr, s11_2Ext:$off),
2052 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
2053 (ins IntRegs:$Rz, ModRegs:$Mu),
2074 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
2075 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
2079 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
2080 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
2081 def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>;
2082 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
2086 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
2099 : LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_),
2100 (ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu),
2129 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
2130 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
2158 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
2159 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
2164 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
2165 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2166 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
2167 def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>;
2172 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2195 (ins IntRegs:$src),
2207 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
2214 : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt),
2230 def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>;
2242 <(outs RC:$dst, IntRegs:$_dst_),
2243 (ins IntRegs:$Rz, ModRegs:$Mu),
2265 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
2266 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
2267 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
2268 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
2269 def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
2270 def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
2271 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2313 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2399 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2491 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2625 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2656 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2660 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2700 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2719 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32ImmPred:$u8))]>;
2722 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2727 def M2_mpyui : MInst<(outs IntRegs:$dst),
2728 (ins IntRegs:$src1, IntRegs:$src2),
2738 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2740 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2747 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2768 : MInst < (outs IntRegs:$dst),
2769 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2791 [(set (i32 IntRegs:$dst),
2792 (add (mul IntRegs:$src2, u32ImmPred:$src3),
2793 IntRegs:$src1))]>, ImmRegRel;
2796 [(set (i32 IntRegs:$dst),
2797 (add (mul IntRegs:$src2, IntRegs:$src3),
2798 IntRegs:$src1))]>, ImmRegRel;
2804 [(set (i32 IntRegs:$dst),
2805 (add (add (i32 IntRegs:$src2), s32ImmPred:$src3),
2806 (i32 IntRegs:$src1)))]>, ImmRegRel;
2809 [(set (i32 IntRegs:$dst),
2810 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2811 (i32 IntRegs:$src1)))]>, ImmRegRel;
2829 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2830 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2833 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2834 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3023 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
3086 (ins IntRegs:$Rs, IntRegs:$Rt),
3114 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
3187 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
3188 (i64 (anyext (i32 IntRegs:$src2))))),
3189 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
3191 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
3192 (i64 (sext (i32 IntRegs:$src2))))),
3193 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
3203 (mul (i64 (sext (i32 IntRegs:$src2))),
3204 (i64 (sext (i32 IntRegs:$src3)))))),
3205 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3208 (mul (i64 (sext (i32 IntRegs:$src2))),
3209 (i64 (sext (i32 IntRegs:$src3)))))),
3210 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3213 (mul (i64 (anyext (i32 IntRegs:$src2))),
3214 (i64 (anyext (i32 IntRegs:$src3)))))),
3215 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3218 (mul (i64 (zext (i32 IntRegs:$src2))),
3219 (i64 (zext (i32 IntRegs:$src3)))))),
3220 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3223 (mul (i64 (anyext (i32 IntRegs:$src2))),
3224 (i64 (anyext (i32 IntRegs:$src3)))))),
3225 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3228 (mul (i64 (zext (i32 IntRegs:$src2))),
3229 (i64 (zext (i32 IntRegs:$src3)))))),
3230 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3268 : STInst <(outs IntRegs:$_dst_),
3269 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
3304 : STInst <(outs IntRegs:$_dst_),
3305 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
3359 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
3362 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
3365 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
3371 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
3388 : STInst <(outs IntRegs:$_dst_),
3389 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
3410 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
3411 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
3412 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
3414 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
3420 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
3456 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
3516 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
3519 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
3522 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
3529 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
3549 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3550 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
3552 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3553 (MI IntRegs:$Rs, 0, Value:$Rt)>;
3568 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3569 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
3572 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3573 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
3634 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
3640 (ins IntRegs:$addr, s11_2Ext:$off, ModRegs:$src1),
3663 : STInst <(outs IntRegs:$_dst_),
3664 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3691 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3693 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3695 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3697 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3705 : NVInst < (outs IntRegs:$_dst_),
3706 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3741 : STInst <(outs IntRegs:$_dst_),
3742 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3764 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3765 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3766 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3768 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3777 : NVInst <(outs IntRegs:$_dst_),
3778 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3810 <(outs IntRegs:$_dst_),
3811 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3833 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3836 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3839 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3843 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3852 : NVInst <(outs IntRegs:$_dst_),
3853 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3907 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3911 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3915 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
3984 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
3985 (i32 (sub 0, (i32 IntRegs:$src))),
3986 (i32 IntRegs:$src))),
3987 (A2_abs IntRegs:$src)>;
3990 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
3991 (i32 IntRegs:$src)),
3992 (sra (i32 IntRegs:$src), (i32 31)))),
3993 (A2_abs IntRegs:$src)>;
4019 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
4023 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
4028 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
4033 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
4055 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
4060 def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src),
4066 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
4133 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
4137 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
4169 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
4185 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
4205 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
4206 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4207 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4208 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4209 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4210 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4211 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
4212 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4213 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4214 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4215 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4216 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
4222 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
4239 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4257 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
4258 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4259 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
4260 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4261 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
4262 (S2_tstbit_i IntRegs:$Rs, 0)>;
4269 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
4286 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4306 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
4307 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
4308 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
4309 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
4313 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
4314 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
4331 def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add (i32 IntRegs:$b), 3))),
4333 (i32 (zextloadi8 (add (i32 IntRegs:$b), 2)))),
4335 (shl (i32 (zextloadi8 (add (i32 IntRegs:$b), 1))), (i32 8))),
4336 (zextloadi8 (i32 IntRegs:$b))),
4337 (A2_swiz (L2_loadri_io IntRegs:$b, 0))>;
4349 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
4363 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
4382 def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32ImmPred:$Off))),
4383 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
4384 def: Pat<(i1 (load (i32 IntRegs:$Rs))),
4385 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
4433 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
4434 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
4436 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
4437 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
4500 def TFR_FI : ALU32_ri<(outs IntRegs:$Rd),
4501 (ins IntRegs:$fi, s32Imm:$off), "">;
4502 def TFR_FIA : ALU32_ri<(outs IntRegs:$Rd),
4503 (ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">;
4533 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
4605 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
4632 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2),
4675 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
4677 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
4678 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
4697 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
4699 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
4700 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
4704 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
4725 : ALU32_ri<(outs IntRegs:$dst),
4748 def LO_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4753 def HI_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4759 def HI_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4765 def LO_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4771 def HI_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4777 def LO_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4785 def CONST32 : CONSTLDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4787 [(set (i32 IntRegs:$dst),
4791 def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
4793 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4861 def: Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4862 (TCRETURNr IntRegs:$dst)>;
4865 def: Pat<(and (i32 IntRegs:$src1), 65535),
4866 (A2_zxth IntRegs:$src1)>;
4869 def: Pat<(and (i32 IntRegs:$src1), 255),
4870 (A2_zxtb IntRegs:$src1)>;
4885 (i32 IntRegs:$src3)),
4886 (C2_muxir PredRegs:$src1, IntRegs:$src3, s32ImmPred:$src2)>;
4890 def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32ImmPred:$src3),
4891 (C2_muxri PredRegs:$src1, s32ImmPred:$src3, IntRegs:$src2)>;
4911 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4913 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4916 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4918 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4927 def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset),
4928 (J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ImmPred:$src2)),
4956 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
4957 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
4960 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4961 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
4971 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
4972 (C2_not (C2_cmpeqi IntRegs:$src1, s32ImmPred:$src2))>;
4985 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4986 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
4990 def: Pat<(i1 (setge (i32 IntRegs:$src1), s32ImmPred:$src2)),
4991 (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
5002 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
5003 (C2_not (C2_cmpgti IntRegs:$src1,
5007 def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)),
5008 (C2_cmpeq IntRegs:$src1, IntRegs:$src1)>;
5011 def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32ImmPred:$src2)),
5012 (C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32ImmPred:$src2))>;
5015 def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32ImmPred:$src2)),
5016 (C2_cmpgtui IntRegs:$src1, u32ImmPred:$src2)>;
5078 def ALLOCA: ALU32Inst<(outs IntRegs:$Rd),
5079 (ins IntRegs:$Rs, u32Imm:$A), "",
5080 [(set (i32 IntRegs:$Rd),
5081 (HexagonALLOCA (i32 IntRegs:$Rs), (i32 imm:$A)))]>;
5084 def ALIGNA : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>;
5089 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
5091 [(set (i32 IntRegs:$dst),
5092 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
5095 def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
5096 (i32 IntRegs:$src1)>;
5118 : SInst_acc<(outs IntRegs:$Rx),
5119 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
5121 [(set (i32 IntRegs:$Rx),
5122 (OpNode2 (i32 IntRegs:$src1),
5123 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
5148 : SInst_acc<(outs IntRegs:$Rx),
5149 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
5151 [(set (i32 IntRegs:$Rx),
5152 (OpNode2 (i32 IntRegs:$src1),
5153 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
5206 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
5210 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
5363 (ins RC:$src1, IntRegs:$src2),
5372 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
5382 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
5383 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
5384 (i32 IntRegs:$src2)))]>;
5388 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5394 (i32 IntRegs:$src2)))]>;
5427 : SInst < (outs IntRegs:$Rd),
5428 (ins DoubleRegs:$Rss, IntRegs:$Rt),
5492 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5530 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5531 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5574 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5632 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5655 def: Pat<(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5656 (M2_mpysin IntRegs:$src1, u8ImmPred:$src2)>;
5664 : SInst <(outs IntRegs:$Rx),
5665 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5695 : SInst <(outs IntRegs:$Rx),
5696 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, u5Imm:$u5),