Lines Matching refs:IntRegs
165 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
194 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
196 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
197 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
199 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
200 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
202 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
203 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
205 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
210 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
245 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
273 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
274 (A4_rcmpeqi IntRegs:$Rs, s32ImmPred:$s8)>;
275 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
276 (A4_rcmpneqi IntRegs:$Rs, s32ImmPred:$s8)>;
279 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
280 (i32 IntRegs:$src1))), 0)))),
281 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
311 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
315 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
321 def: Pat<(HexagonCOMBINE IntRegs:$r, s32ImmPred:$i),
322 (A4_combineri IntRegs:$r, s32ImmPred:$i)>;
324 def: Pat<(HexagonCOMBINE s32ImmPred:$i, IntRegs:$r),
325 (A4_combineir s32ImmPred:$i, IntRegs:$r)>;
373 def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))),
374 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
375 def: Pat<(VT (Load (i32 IntRegs:$Rs))),
376 (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
389 def: Pat<(i64 (anyext (i32 IntRegs:$src1))), (Zext64 IntRegs:$src1)>;
397 LDInst<(outs RC:$dst1, IntRegs:$dst2),
417 def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
418 def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
422 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
423 def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
424 def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>;
425 def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
429 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
450 : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3),
473 def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>;
474 def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>;
480 def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
481 def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>;
482 def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>;
483 def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
489 def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
499 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
501 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3)>;
502 def : Pat <(VT (ldOp (add IntRegs:$src1,
504 (MI IntRegs:$src1, 0, tglobaladdr:$src2)>;
506 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
508 (MI IntRegs:$src1, u2ImmPred:$src2, tconstpool:$src3)>;
509 def : Pat <(VT (ldOp (add IntRegs:$src1,
511 (MI IntRegs:$src1, 0, tconstpool:$src2)>;
513 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
515 (MI IntRegs:$src1, u2ImmPred:$src2, tjumptable:$src3)>;
516 def : Pat <(VT (ldOp (add IntRegs:$src1,
518 (MI IntRegs:$src1, 0, tjumptable:$src2)>;
539 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
566 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
616 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
617 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
621 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
622 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
626 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
635 : Pat<(VT (Load (add (i32 IntRegs:$Rs),
636 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2))))),
637 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
653 : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
654 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
672 def: Pat<(i64 (zext (i32 IntRegs:$src1))),
673 (Zext64 IntRegs:$src1)>;
690 : STInst<(outs IntRegs:$dst),
713 def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
714 def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
716 def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>;
719 def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs,
729 : NVInst <(outs IntRegs:$dst),
730 (ins u6Ext:$addr, IntRegs:$src),
760 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, RC:$src4),
788 def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
789 def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
791 def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011,
793 def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
801 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
803 (MI IntRegs:$src1, u2ImmPred:$src2, u32ImmPred:$src3, RC:$src4)>;
806 (add (shl IntRegs:$src1, u2ImmPred:$src2),
808 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
811 (add IntRegs:$src1, (HexagonCONST32 tglobaladdr:$src3))),
812 (MI IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
816 defm : T_StoreAbsReg_Pats <S4_storeri_ur, IntRegs, i32, store>;
817 defm : T_StoreAbsReg_Pats <S4_storerb_ur, IntRegs, i32, truncstorei8>;
818 defm : T_StoreAbsReg_Pats <S4_storerh_ur, IntRegs, i32, truncstorei16>;
825 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
857 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
888 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
924 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
951 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
1020 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
1021 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
1024 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
1025 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
1028 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
1029 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
1035 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
1039 : Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs),
1040 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2)))),
1041 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
1067 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
1096 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
1262 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1298 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1359 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1363 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1367 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1376 def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
1382 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_),
1383 (ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3),
1412 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1413 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1446 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1447 (ins PredRegs:$src1, IntRegs:$src2,
1448 ImmOp:$offset, IntRegs:$src3),
1512 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1513 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1566 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1641 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1699 (ins IntRegs:$src1, brtarget:$offset),
1751 (ins IntRegs:$Rs),
1770 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1876 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1893 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1894 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1896 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1897 (add (i32 IntRegs:$Ru), s32ImmPred:$s6)))],
1917 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1918 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1938 def: Pat<(add (i32 IntRegs:$src1), (sub s32ImmPred:$src2,
1939 (i32 IntRegs:$src3))),
1940 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1943 def: Pat<(sub (add (i32 IntRegs:$src1), s32ImmPred:$src2),
1944 (i32 IntRegs:$src3)),
1945 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1948 def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)),
1950 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1970 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
2020 (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2044 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2066 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
2099 ALU64Inst<(outs IntRegs:$Rx),
2100 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
2102 [(set (i32 IntRegs:$Rx),
2103 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s32ImmPred:$s10)))] ,
2121 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2137 (ins IntRegs:$Rs, IntRegs:$Rt),
2153 (ins IntRegs:$Rs, IntRegs:$Rt),
2168 def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd),
2169 (ins IntRegs:$Rs, IntRegs:$Rt),
2184 def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd),
2185 (ins IntRegs:$Rs, IntRegs:$Rt),
2232 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2,
2233 (not IntRegs:$src3)))),
2234 (i32 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3))>;
2244 : MInst_acc <(outs IntRegs:$Rx),
2245 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
2247 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
2248 (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10)))],
2333 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2348 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2368 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
2369 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
2370 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
2371 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
2378 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2379 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2382 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2383 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2413 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2414 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2416 [(set (i32 IntRegs:$Rd),
2417 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2439 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2440 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2442 [(set (i32 IntRegs:$Rd),
2443 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u32ImmPred:$u6))],
2463 : ALU64Inst <(outs IntRegs:$dst), ins,
2466 [(set (i32 IntRegs:$dst),
2467 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2489 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2494 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2498 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2499 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2501 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2502 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2624 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2626 [(set (i32 IntRegs:$Rd),
2665 (S4_addi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2667 (S4_addi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2669 (S4_subi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2671 (S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2681 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2682 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2687 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2723 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
2762 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2764 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2765 (i32 IntRegs:$Rt)))],
2865 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2896 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2965 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2966 IntRegs:$addr),
2967 (MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
2970 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ImmPred:$offset)),
2972 (add IntRegs:$base, ImmPred:$offset)),
2973 (MI IntRegs:$base, ImmPred:$offset, u5ImmPred:$addend)>;
3012 def: Pat<(stOp (add (ldOp IntRegs:$addr), immPred:$subend), IntRegs:$addr),
3013 (MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
3016 def: Pat<(stOp (add (ldOp (add IntRegs:$base, ImmPred:$offset)),
3018 (add IntRegs:$base, ImmPred:$offset)),
3019 (MI IntRegs:$base, ImmPred:$offset, (xformFunc immPred:$subend))>;
3053 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3055 (add IntRegs:$base, extPred:$offset)),
3056 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
3060 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), immPred:$bitend), IntRegs:$addr),
3061 (MI IntRegs:$addr, 0, (xformFunc immPred:$bitend))>;
3105 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), (i32 IntRegs:$addend)),
3106 IntRegs:$addr),
3107 (MI IntRegs:$addr, 0, (i32 IntRegs:$addend))>;
3111 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3112 (i32 IntRegs:$orend)),
3113 (add IntRegs:$base, extPred:$offset)),
3114 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend))>;
3174 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
3175 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
3176 // (C4_cmpltei IntRegs:$src1, s32ImmPred:$src2)>;
3179 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
3180 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
3183 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
3184 (C4_cmpneqi IntRegs:$src1, s32ImmPred:$src2)>;
3210 def: Pat<(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3212 (C2_muxii (A4_cmpbgtui IntRegs:$src1,
3445 : NVInst_V4<(outs), (ins ImmOp:$addr, IntRegs:$src),
3476 : NVInst_V4<(outs), (ins PredRegs:$src1, u32MustExt:$absaddr, IntRegs:$src2),
3544 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3548 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3552 defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
3559 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3585 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3606 def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
3746 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3747 defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3751 defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3752 defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3756 defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3776 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3777 def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3781 def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3782 def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3786 def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3923 def Insert4 : PseudoM<(outs DoubleRegs:$dst), (ins IntRegs:$a, IntRegs:$b,
3924 IntRegs:$c, IntRegs:$d),
3927 (or (or (or (shl (i64 (zext (i32 (and (i32 IntRegs:$b), (i32 65535))))),
3929 (i64 (zext (i32 (and (i32 IntRegs:$a), (i32 65535)))))),
3930 (shl (i64 (anyext (i32 (and (i32 IntRegs:$c), (i32 65535))))),
3932 (shl (i64 (anyext (i32 IntRegs:$d))), (i32 48))))]>;
3980 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
3986 (ins DoubleRegs:$Rs, IntRegs:$Rt),
4012 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
4014 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
4027 def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)),
4028 (Y2_dcfetchbo IntRegs:$Rs, u11_3ImmPred:$u11_3)>;
4039 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4085 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4139 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4194 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4247 (outs IntRegs:$Rd),
4267 (outs IntRegs:$Rd),
4268 (ins IntRegs:$Rs, brtarget:$r9_2),