Lines Matching refs:IntRegs
165 def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)),
166 (V6_vS32b_ai IntRegs:$addr, 0,
171 def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
173 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
176 def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)),
177 (V6_vS32b_ai_128B IntRegs:$addr, 0,
182 def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
184 (v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)),
190 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>,
192 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
193 (!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>,
218 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
219 (MI VecDblRegs:$src1, IntRegs:$src2)>,
222 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2),
223 (!cast<InstHexagon>(MI#"_128B")VecDblRegs128B:$src1, IntRegs:$src2)>,
228 def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
229 (MI VectorRegs:$src1, IntRegs:$src2)>,
232 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2),
233 (!cast<InstHexagon>(MI#"_128B")VectorRegs128B:$src1, IntRegs:$src2)>,
274 def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
275 (MI VecPredRegs:$src1, IntRegs:$src2)>,
279 IntRegs:$src2),
281 IntRegs:$src2)>,
298 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
299 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
304 IntRegs:$src3),
307 IntRegs:$src3)>,
312 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
313 (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
318 IntRegs:$src3),
321 IntRegs:$src3)>,
326 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
327 (MI VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
332 IntRegs:$src3),
335 IntRegs:$src3)>,
340 def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
341 (MI VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
346 IntRegs:$src3),
349 IntRegs:$src3)>,
396 def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
397 (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>,
402 IntRegs:$src3),
405 IntRegs:$src3)>,
411 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
412 (MI VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
417 IntRegs:$src3),
420 IntRegs:$src3)>,
437 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3),
438 (MI VecDblRegs:$src1, IntRegs:$src2, imm:$src3)>,
442 IntRegs:$src2, imm:$src3),
444 IntRegs:$src2, imm:$src3)>,
449 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4),
450 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4)>,
455 IntRegs:$src3, imm:$src4),
458 IntRegs:$src3, imm:$src4)>,
464 IntRegs:$src4),
466 IntRegs:$src4)>,
472 IntRegs:$src4),
476 IntRegs:$src4)>,
482 IntRegs:$src4),
484 IntRegs:$src4)>,
490 IntRegs:$src4),
494 IntRegs:$src4)>,