Lines Matching refs:RO
186 RegisterOperand RO> :
187 InstSE<(outs), (ins RO:$rs, opnd:$offset),
196 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
198 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
200 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
206 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
208 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
210 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
229 class MovePMM16<string opstr, RegisterOperand RO> :
230 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
267 class LLBaseMM<string opstr, RegisterOperand RO> :
268 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
274 class LLEBaseMM<string opstr, RegisterOperand RO> :
275 InstSE<(outs RO:$rt), (ins mem_simm9:$addr),
281 class SCBaseMM<string opstr, RegisterOperand RO> :
282 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
289 class SCEBaseMM<string opstr, RegisterOperand RO> :
290 InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
297 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
299 InstSE<(outs RO:$rt), (ins MO:$addr),
301 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
307 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
310 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
312 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
316 class AndImmMM16<string opstr, RegisterOperand RO,
318 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
321 class LogicRMM16<string opstr, RegisterOperand RO,
324 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
326 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
331 class NotMM16<string opstr, RegisterOperand RO> :
332 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
334 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
336 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
338 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
341 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
343 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
350 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
359 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
361 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
368 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
370 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
376 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
378 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
385 class AddImmUR2<string opstr, RegisterOperand RO> :
386 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
392 class AddImmUS5<string opstr, RegisterOperand RO> :
393 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
398 class AddImmUR1SP<string opstr, RegisterOperand RO> :
399 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
406 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
407 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
413 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
415 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
421 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
422 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
428 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
429 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
430 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>, PredicateControl {
437 class JumpRegMM16<string opstr, RegisterOperand RO> :
438 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
456 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
457 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
465 class JumpRegCMM16<string opstr, RegisterOperand RO> :
466 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
480 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
481 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
497 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
498 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
502 RegisterOperand RO> :
503 InstSE<(outs), (ins RO:$rs, opnd:$offset),
507 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
510 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
517 class AddImmUPC<string opstr, RegisterOperand RO> :
518 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),