Lines Matching refs:TempReg
349 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP() local
350 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
380 unsigned TempReg = createResultReg(RC); in materializeGV() local
381 emitInst(Mips::ADDiu, TempReg) in materializeGV()
384 DestReg = TempReg; in materializeGV()
610 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
611 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
612 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
616 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
617 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
618 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); in emitCmp()
630 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
631 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
632 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
636 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
637 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
638 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
650 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
651 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
652 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
656 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
657 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
658 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
1009 unsigned TempReg = createResultReg(RC); in selectSelect() local
1011 if (!ResultReg || !TempReg) in selectSelect()
1014 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg); in selectSelect()
1016 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg); in selectSelect()
1075 unsigned TempReg = createResultReg(&Mips::FGR32RegClass); in selectFPToInt() local
1079 emitInst(Opc, TempReg).addReg(SrcReg); in selectFPToInt()
1080 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
1365 unsigned TempReg[3]; in fastLowerIntrinsicCall() local
1367 TempReg[i] = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1368 if (TempReg[i] == 0) in fastLowerIntrinsicCall()
1371 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1372 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1373 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]); in fastLowerIntrinsicCall()
1374 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF); in fastLowerIntrinsicCall()
1380 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall() local
1381 emitInst(Mips::WSBH, TempReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1382 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16); in fastLowerIntrinsicCall()
1386 unsigned TempReg[8]; in fastLowerIntrinsicCall() local
1388 TempReg[i] = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1389 if (TempReg[i] == 0) in fastLowerIntrinsicCall()
1393 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1394 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1395 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00); in fastLowerIntrinsicCall()
1396 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]); in fastLowerIntrinsicCall()
1398 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00); in fastLowerIntrinsicCall()
1399 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8); in fastLowerIntrinsicCall()
1401 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1402 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]); in fastLowerIntrinsicCall()
1403 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]); in fastLowerIntrinsicCall()
1588 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitIntSExt32r1() local
1589 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1590 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()
1723 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in selectShift() local
1724 if (!TempReg) in selectShift()
1729 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt)) in selectShift()
1732 Op0Reg = TempReg; in selectShift()
1847 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in getRegEnsuringSimpleIntegerWidening() local
1848 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned)) in getRegEnsuringSimpleIntegerWidening()
1850 VReg = TempReg; in getRegEnsuringSimpleIntegerWidening()
1857 unsigned TempReg = in simplifyAddress() local
1860 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg()); in simplifyAddress()