Lines Matching refs:tr2
1491 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
1493 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
1495 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
1504 TypedReg tr2, bits<4> type, bits<4> modifier = 0,
1506 def "" : UnaryVRRa<mnemonic, opcode, operator, tr1, tr2, type, 0, modifier>;
1508 def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 0,
1743 TypedReg tr1, TypedReg tr2, bits<4> type>
1744 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
1746 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1752 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
1753 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
1755 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1769 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
1771 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1773 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1774 (tr2.vt tr2.op:$V3))))]> {
1784 TypedReg tr2, bits<4> type,
1786 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, modifier>;
1788 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1793 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
1795 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1797 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1798 (tr2.vt tr2.op:$V3))))]> {
1807 TypedReg tr2, bits<4> type, bits<4> m5,
1809 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, modifier>;
1811 def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1822 TypedReg tr1, TypedReg tr2, bits<4> type>
1823 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
1825 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
2098 TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
2099 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
2101 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2108 TypedReg tr1, TypedReg tr2, bits<4> type>
2110 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
2112 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2113 (tr2.vt tr2.op:$V3),
2119 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
2121 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
2123 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2131 TypedReg tr1, TypedReg tr2, bits<4> type,
2134 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
2136 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2137 (tr2.vt tr2.op:$V3),
2146 TypedReg tr2, bits<4> type, bits<4> m5or> {
2147 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
2150 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2151 tr2.op:$V3, 0)>;
2153 def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2156 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2157 tr2.op:$V3, 0)>;
2161 TypedReg tr1, TypedReg tr2>
2163 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
2165 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2166 (tr2.vt tr2.op:$V3),
2173 TypedReg tr1, TypedReg tr2, bits<4> type = 0>
2175 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
2177 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2178 (tr2.vt tr2.op:$V3),
2185 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
2187 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
2189 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2190 (tr2.vt tr2.op:$V3),
2197 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
2199 (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
2201 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2221 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
2223 (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
2225 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2235 TypedReg tr1, TypedReg tr2, bits<4> type>
2237 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
2239 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2240 (tr2.vt tr2.op:$V2),
2241 (tr2.vt tr2.op:$V3),
2249 SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
2252 (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6),
2254 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2255 (tr2.vt tr2.op:$V3),
2256 (tr2.vt tr2.op:$V4),
2265 TypedReg tr2, bits<4> type, bits<4> m6or> {
2266 def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
2269 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2270 tr2.op:$V3, tr2.op:$V4, 0)>;
2272 def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2275 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2276 tr2.op:$V3, tr2.op:$V4, 0)>;
2603 class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
2604 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
2605 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;