660     setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);  in X86TargetLowering()
767     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);  in X86TargetLowering()
768     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Custom);  in X86TargetLowering()
769     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f32, Custom);  in X86TargetLowering()
813       setOperationAction(ISD::INSERT_VECTOR_ELT,  VT, Custom);  in X86TargetLowering()
929     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i8, Custom);  in X86TargetLowering()
1108       setOperationAction(ISD::INSERT_VECTOR_ELT,  VT, Custom);  in X86TargetLowering()
1302     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i1, Custom);  in X86TargetLowering()
1303     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i1, Custom);  in X86TargetLowering()
1396       setOperationAction(ISD::INSERT_VECTOR_ELT,   VT, Custom);  in X86TargetLowering()
1455     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v32i1, Custom);  in X86TargetLowering()
1456     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v64i1, Custom);  in X86TargetLowering()
1457     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v32i16, Custom);  in X86TargetLowering()
1458     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v64i8, Custom);  in X86TargetLowering()
5287         V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,  in LowerBuildVectorv16i8()
5324         V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,  in LowerBuildVectorv16i8()
5354       V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,  in LowerBuildVectorv8i16()
5939   if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))  in buildFromShuffleMostly()
5999     NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),  in buildFromShuffleMostly()
6094     DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,  in LowerBUILD_VECTORvXi1()
6667           return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,  in LowerBUILD_VECTOR()
6856         Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,  in LowerBUILD_VECTOR()
12539     SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,  in InsertBitToMaskVector()
12612     V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,  in LowerINSERT_VECTOR_ELT()
16463       Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,  in LowerExtendedLoad()
19959         } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {  in LowerScalarVariableShift()
21679   case ISD::INSERT_VECTOR_ELT:  return LowerINSERT_VECTOR_ELT(Op, DAG);  in LowerOperation()
28914   SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, ML->getSrc0(),  in reduceMaskedLoadToScalarLoad()