Lines Matching refs:SIGN_EXTEND
688 setOperationAction(ISD::SIGN_EXTEND, VT, Expand); in X86TargetLowering()
997 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom); in X86TargetLowering()
998 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); in X86TargetLowering()
999 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in X86TargetLowering()
1271 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1272 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1273 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom); in X86TargetLowering()
1274 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom); in X86TargetLowering()
1275 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in X86TargetLowering()
1277 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom); in X86TargetLowering()
1278 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom); in X86TargetLowering()
1446 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom); in X86TargetLowering()
1448 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom); in X86TargetLowering()
1453 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
1657 setTargetDAGCombine(ISD::SIGN_EXTEND); in X86TargetLowering()
2089 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2094 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
3107 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); in LowerCall()
3115 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); in LowerCall()
12094 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1); in lower1BitVectorShuffle()
12103 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2); in lower1BitVectorShuffle()
13351 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src)); in LowerSINT_TO_FP()
14110 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In); in LowerTruncateVecI1()
14876 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in EmitCmp()
16236 ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in LowerExtended1BitVectorLoad()
17692 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask); in LowerINTRINSIC_WO_CHAIN()
19328 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A), in LowerMUL()
19329 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B))); in LowerMUL()
19825 return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, CMP); in LowerScalarImmediateShift()
20341 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerShift()
21452 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index); in LowerMSCATTER()
21461 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index); in LowerMSCATTER()
21577 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index); in LowerMGATHER()
21590 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index); in LowerMGATHER()
21695 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG); in LowerOperation()
26353 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && in combineExtractVectorElt()
26604 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond); in combineSelect()
27517 return DAG.getNode((Mode == MULU8) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND, in reduceVMULWidth()
27714 } else if (N00.getOpcode() == ISD::SIGN_EXTEND && in combineShiftLeft()
27886 case ISD::SIGN_EXTEND: in combineCompareEqual()
28007 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node"); in WidenMaskArithmetic()
28068 case ISD::SIGN_EXTEND: in WidenMaskArithmetic()
29974 N0.getOpcode() == ISD::SIGN_EXTEND)) { in combineSignExtendInReg()
29986 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp); in combineSignExtendInReg()
30033 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0); in promoteSextBeforeAddNSW()
30051 if (!((OpcodeN == ISD::SIGN_EXTEND && OpcodeN0 == ISD::SDIVREM) || in getDivRem8()
30077 if (Opcode != ISD::SIGN_EXTEND && Opcode != ISD::ZERO_EXTEND) in combineToExtendVectorInReg()
30134 return Opcode == ISD::SIGN_EXTEND in combineToExtendVectorInReg()
30152 SrcVec = Opcode == ISD::SIGN_EXTEND in combineToExtendVectorInReg()
30314 (LHS.getOpcode() == ISD::SIGN_EXTEND) && in combineSetCC()
30323 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) && in combineSetCC()
30535 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0); in combineSIntToFP()
30988 case ISD::SIGN_EXTEND: return combineSext(N, DAG, DCI, Subtarget); in PerformDAGCombine()
31047 case ISD::SIGN_EXTEND: in isTypeDesirableForOp()
31086 case ISD::SIGN_EXTEND: in IsDesirableToPromoteOp()