Lines Matching refs:hasInt256
947 bool HasInt256 = Subtarget.hasInt256(); in X86TargetLowering()
4687 if (!Subtarget.hasInt256() && NumElts == 8) { in getOnesVector()
5799 if (!Subtarget.hasInt256()) in LowerVectorBroadcast()
5876 if (!IsLoad && Subtarget.hasInt256() && in LowerVectorBroadcast()
5890 if (Subtarget.hasInt256() && Ld.getValueType().isInteger()) { in LowerVectorBroadcast()
6567 (VT == MVT::v8i32 && Subtarget.hasInt256())) in materializeVectorConstant()
12433 (VecVT.is256BitVector() && Subtarget.hasInt256() && in LowerEXTRACT_VECTOR_ELT()
14005 if (Subtarget.hasInt256()) in LowerAVXExtend()
14150 if (Subtarget.hasInt256()) { in LowerTRUNCATE()
14171 if (Subtarget.hasInt256()) { in LowerTRUNCATE()
15347 if (VT.is256BitVector() && !Subtarget.hasInt256()) in LowerVSETCC()
16067 !(VT.is256BitVector() && Subtarget.hasInt256())) in LowerSIGN_EXTEND_VECTOR_INREG()
16131 if (Subtarget.hasInt256()) in LowerSIGN_EXTEND()
16355 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget.hasInt256()) { in LowerExtendedLoad()
19108 if (VT.is256BitVector() && !Subtarget.hasInt256()) { in LowerVectorCTLZ()
19303 if (VT.is256BitVector() && !Subtarget.hasInt256()) in LowerMUL()
19312 if (Subtarget.hasInt256()) { in LowerMUL()
19452 if (VT.is256BitVector() && !Subtarget.hasInt256()) in LowerMULH()
19456 assert((VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget.hasInt256())) && in LowerMULH()
19471 if (Subtarget.hasInt256()) { in LowerMULH()
19619 if (VT.is256BitVector() && !Subtarget.hasInt256()) { in LowerMUL_LOHI()
19637 (VT == MVT::v8i32 && Subtarget.hasInt256())); in LowerMUL_LOHI()
19719 (VT.is256BitVector() && Subtarget.hasInt256()); in SupportedVectorShiftWithImm()
19739 if (!Subtarget.hasInt256() || VT.getScalarSizeInBits() < 16) in SupportedVectorVarShift()
19805 if ((VT == MVT::v2i64 || (Subtarget.hasInt256() && VT == MVT::v4i64)) && in LowerScalarImmediateShift()
19810 (Subtarget.hasInt256() && VT == MVT::v32i8) || in LowerScalarImmediateShift()
19868 (VT == MVT::v2i64 || (Subtarget.hasInt256() && VT == MVT::v4i64))) { in LowerScalarImmediateShift()
20056 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget.hasInt256())) && in LowerShift()
20071 (Subtarget.hasInt256() && VT == MVT::v16i16))) { in LowerShift()
20228 (VT == MVT::v32i8 && Subtarget.hasInt256() && !Subtarget.hasXOP())) { in LowerShift()
20338 if (Subtarget.hasInt256() && VT == MVT::v8i16) { in LowerShift()
20348 if (Subtarget.hasInt256() && !Subtarget.hasXOP() && VT == MVT::v16i16) { in LowerShift()
21031 if (VT.is256BitVector() && !Subtarget.hasInt256()) { in LowerVectorCTPOP()
21134 if (VT.is256BitVector() && !Subtarget.hasInt256()) { in LowerBITREVERSE()
22399 if (Subtarget.hasInt256() && (Bits == 32 || Bits == 64)) in isVectorShiftByScalarCheap()
27806 (!Subtarget.hasInt256() || in performShiftToAllZeros()
28304 if (!((VT == MVT::v2i64) || (VT == MVT::v4i64 && Subtarget.hasInt256()))) in combineLogicBlendIntoPBLENDV()
29979 if (N00.getOpcode() == ISD::LOAD && Subtarget.hasInt256()) in combineSignExtendInReg()
30100 if (Subtarget.hasInt256() && DAG.getTargetLoweringInfo().isTypeLegal(VT) && in combineToExtendVectorInReg()
30132 (VT.is256BitVector() && Subtarget.hasInt256())) { in combineToExtendVectorInReg()
30141 if (!Subtarget.hasInt256() && !(VT.getSizeInBits() % 128)) { in combineToExtendVectorInReg()
30776 (Subtarget.hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && in combineAdd()
30809 (Subtarget.hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && in combineSub()