Lines Matching refs:MRMSrcReg
246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
267 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
515 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
777 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1352 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1359 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1368 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1374 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1444 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1456 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1469 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1608 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1622 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1787 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1804 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1816 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1823 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1832 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1839 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1852 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1879 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1901 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1916 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1934 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1943 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1953 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1969 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1984 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2003 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2010 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2016 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2024 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2077 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2097 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2113 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2127 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2134 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2143 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2158 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2164 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2173 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2206 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2221 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2234 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2294 def rr : SIi8<0xC2, MRMSrcReg,
2307 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2342 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2382 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2449 def rri : PIi8<0xC2, MRMSrcReg,
2462 def rri_alt : PIi8<0xC2, MRMSrcReg,
2547 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2630 def rr : PI<opc, MRMSrcReg,
2713 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2747 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3280 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3292 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3335 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3343 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3392 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3402 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3414 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3428 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3438 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3450 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3722 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3725 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3728 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3731 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3794 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3797 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3869 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3910 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3941 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4214 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4232 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4250 def ri : Ii8<0x70, MRMSrcReg,
4297 def rr : PDI<opc, MRMSrcReg,
4320 def Yrr : PDI<opc, MRMSrcReg,
4340 def rr : SS48I<opc, MRMSrcReg,
4363 def Yrr : SS48I<opc, MRMSrcReg,
4425 def rr : PDI<opc, MRMSrcReg,
4445 def Yrr : PDI<opc, MRMSrcReg,
4528 def rri : Ii8<0xC4, MRMSrcReg,
4551 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4557 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4579 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4586 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4593 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4607 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4613 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4620 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4625 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4639 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4650 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4660 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4665 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4675 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4685 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4694 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4704 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4993 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4999 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5041 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5101 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5115 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5201 def rr : I<0xD0, MRMSrcReg,
5280 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5297 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5358 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5375 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5498 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5521 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5543 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5675 def rri : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5695 def Yrri : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5785 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
6191 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6217 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6243 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6274 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6337 def PSr : SS4AIi8<opcps, MRMSrcReg,
6356 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6381 def SSr : SS4AIi8<opcss, MRMSrcReg,
6392 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6416 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6427 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6595 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6604 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6615 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6628 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6656 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6667 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6679 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6696 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6725 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6750 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6883 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6911 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7017 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7165 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7281 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7332 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7369 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7406 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7444 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7472 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7516 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7534 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7571 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7613 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7625 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7638 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7651 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7670 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7687 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7738 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7744 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7749 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7794 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7842 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
8031 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8043 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8110 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8174 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8255 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8284 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8294 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8446 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8471 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8499 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8536 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8712 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8725 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),