Lines Matching refs:RIP
148 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
345 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
346 // RIP isn't really a register and it can't be used anywhere except in an
350 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
376 R8, R9, R11, RIP)>;
378 R8, R9, R10, R11, RIP)>;
396 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
406 // GR64_NOSP - GR64 registers except RSP (and RIP).
407 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
421 // In such cases, it is fine to use RIP as we are sure the 32 high
422 // bits are not set. We do not need variants for NOSP as RIP is not
424 // RIP is not spilled anywhere for now, so stick to 32-bit alignment
429 def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>;