Lines Matching refs:REG

8 ; CHECK: add [[REG:w[0-9]+]], w0, #1
9 ; CHECK: sbfiz w0, [[REG]], #4, #8
20 ; CHECK: add [[REG:w[0-9]+]], w0, #1
21 ; CHECK: sbfx w0, [[REG]], #4, #4
32 ; CHECK: add [[REG:w[0-9]+]], w0, #1
33 ; CHECK: sbfiz w0, [[REG]], #8, #8
44 ; CHECK: add [[REG:w[0-9]+]], w0, #1
45 ; CHECK: sxtb [[REG]], [[REG]]
46 ; CHECK: asr w0, [[REG]], #8
57 ; CHECK: add [[REG:w[0-9]+]], w0, #1
58 ; CHECK: sbfiz w0, [[REG]], #4, #8
68 ; CHECK: add [[REG:w[0-9]+]], w0, #1
69 ; CHECK: sbfx w0, [[REG]], #4, #4
79 ; CHECK: add [[REG:w[0-9]+]], w0, #1
80 ; CHECK: sbfiz w0, [[REG]], #8, #8
90 ; CHECK: add [[REG:w[0-9]+]], w0, #1
91 ; CHECK: sxtb [[REG]], [[REG]]
92 ; CHECK: asr w0, [[REG]], #8
102 ; CHECK: add w[[REG:[0-9]+]], w0, #1
103 ; CHECK: sbfiz x0, x[[REG]], #4, #8
113 ; CHECK: add w[[REG:[0-9]+]], w0, #1
114 ; CHECK: sbfx x0, x[[REG]], #4, #4
124 ; CHECK: add w[[REG:[0-9]+]], w0, #1
125 ; CHECK: sbfiz x0, x[[REG]], #8, #8
135 ; CHECK: add w[[REG:[0-9]+]], w0, #1
136 ; CHECK: sxtb x[[REG]], w[[REG]]
137 ; CHECK: asr x0, x[[REG]], #8
147 ; CHECK: add [[REG:w[0-9]+]], w0, #1
148 ; CHECK: sbfiz w0, [[REG]], #4, #16
158 ; CHECK: add [[REG:w[0-9]+]], w0, #1
159 ; CHECK: sbfx w0, [[REG]], #4, #12
169 ; CHECK: lsl [[REG:w[0-9]+]], w0, #16
170 ; CHECK: add w0, [[REG]], #16, lsl #12
180 ; CHECK: add [[REG:w[0-9]+]], w0, #1
181 ; CHECK: sxth [[REG]], [[REG]]
182 ; CHECK: asr w0, [[REG]], #16
192 ; CHECK: add w[[REG:[0-9]+]], w0, #1
193 ; CHECK: sbfiz x0, x[[REG]], #4, #16
203 ; CHECK: add w[[REG:[0-9]+]], w0, #1
204 ; CHECK: sbfx x0, x[[REG]], #4, #12
214 ; CHECK: add w[[REG:[0-9]+]], w0, #1
215 ; CHECK: sbfiz x0, x[[REG]], #16, #16
225 ; CHECK: add w[[REG:[0-9]+]], w0, #1
226 ; CHECK: sxth x[[REG]], w[[REG]]
227 ; CHECK: asr x0, x[[REG]], #16
237 ; CHECK: add w[[REG:[0-9]+]], w0, #1
238 ; CHECK: sbfiz x0, x[[REG]], #4, #32
248 ; CHECK: add w[[REG:[0-9]+]], w0, #1
249 ; CHECK: sbfx x0, x[[REG]], #4, #28
259 ; CHECK: add w[[REG:[0-9]+]], w0, #1
260 ; CHECK: lsl x0, x[[REG]], #32
270 ; CHECK: add w[[REG:[0-9]+]], w0, #1
271 ; CHECK: sxtw x[[REG]], w[[REG]]
272 ; CHECK: asr x0, x[[REG]], #32