Lines Matching refs:w0
8 ; CHECK: add [[REG:w[0-9]+]], w0, #1
9 ; CHECK: sbfiz w0, [[REG]], #4, #8
20 ; CHECK: add [[REG:w[0-9]+]], w0, #1
21 ; CHECK: sbfx w0, [[REG]], #4, #4
32 ; CHECK: add [[REG:w[0-9]+]], w0, #1
33 ; CHECK: sbfiz w0, [[REG]], #8, #8
44 ; CHECK: add [[REG:w[0-9]+]], w0, #1
46 ; CHECK: asr w0, [[REG]], #8
57 ; CHECK: add [[REG:w[0-9]+]], w0, #1
58 ; CHECK: sbfiz w0, [[REG]], #4, #8
68 ; CHECK: add [[REG:w[0-9]+]], w0, #1
69 ; CHECK: sbfx w0, [[REG]], #4, #4
79 ; CHECK: add [[REG:w[0-9]+]], w0, #1
80 ; CHECK: sbfiz w0, [[REG]], #8, #8
90 ; CHECK: add [[REG:w[0-9]+]], w0, #1
92 ; CHECK: asr w0, [[REG]], #8
102 ; CHECK: add w[[REG:[0-9]+]], w0, #1
113 ; CHECK: add w[[REG:[0-9]+]], w0, #1
124 ; CHECK: add w[[REG:[0-9]+]], w0, #1
135 ; CHECK: add w[[REG:[0-9]+]], w0, #1
147 ; CHECK: add [[REG:w[0-9]+]], w0, #1
148 ; CHECK: sbfiz w0, [[REG]], #4, #16
158 ; CHECK: add [[REG:w[0-9]+]], w0, #1
159 ; CHECK: sbfx w0, [[REG]], #4, #12
169 ; CHECK: lsl [[REG:w[0-9]+]], w0, #16
170 ; CHECK: add w0, [[REG]], #16, lsl #12
180 ; CHECK: add [[REG:w[0-9]+]], w0, #1
182 ; CHECK: asr w0, [[REG]], #16
192 ; CHECK: add w[[REG:[0-9]+]], w0, #1
203 ; CHECK: add w[[REG:[0-9]+]], w0, #1
214 ; CHECK: add w[[REG:[0-9]+]], w0, #1
225 ; CHECK: add w[[REG:[0-9]+]], w0, #1
237 ; CHECK: add w[[REG:[0-9]+]], w0, #1
248 ; CHECK: add w[[REG:[0-9]+]], w0, #1
259 ; CHECK: add w[[REG:[0-9]+]], w0, #1
270 ; CHECK: add w[[REG:[0-9]+]], w0, #1