Lines Matching refs:uminv

5 ; CHECK: uminv.8b        b[[REG:[0-9]+]], v0
10   %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a) nounwind
28 ; CHECK: uminv.4h        h[[REG:[0-9]+]], v0
33   %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a) nounwind
49 ; CHECK: uminv.8h        h[[REG:[0-9]+]], v0
54   %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a) nounwind
70 ; CHECK: uminv.16b        b[[REG:[0-9]+]], v0
75   %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a) nounwind
91 ; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1
95   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a2)
103 ; CHECK: uminv.4h h[[REGNUM:[0-9]+]], v1
107   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a2)
119   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v2i32(<2 x i32> %a2)
126 ; CHECK: uminv.16b b[[REGNUM:[0-9]+]], v1
130   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a2)
138 ; CHECK: uminv.8h h[[REGNUM:[0-9]+]], v1
142   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a2)
150 ; CHECK: uminv.4s s[[REGNUM:[0-9]+]], v1
154   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> %a2)
158 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) nounwind readnone
159 declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>) nounwind readnone
160 declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>) nounwind readnone
161 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) nounwind readnone
162 declare i32 @llvm.aarch64.neon.uminv.i32.v2i32(<2 x i32>) nounwind readnone
163 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>) nounwind readnone