Lines Matching full:float
4 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
12 define amdgpu_vs {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, fl…
13 …call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float …
14 %x = fadd float %3, 1.0
15 %a = insertvalue {float, float} undef, float %x, 0
16 %b = insertvalue {float, float} %a, float %3, 1
17 ret {float, float} %b
28 define amdgpu_vs {float, float, float, float} @vgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i3…
29 …call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float …
30 ret {float, float, float, float} {float 1.0, float 2.0, float 4.0, float -1.0}
46 …float, float, float, float, float} @vgpr_ps_addr0([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, …
51 %f0 = bitcast i32 %i0 to float
52 %f1 = bitcast i32 %i1 to float
53 %f2 = bitcast i32 %i2 to float
54 %f3 = bitcast i32 %i3 to float
55 %r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
56 %r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
57 %r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
58 %r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
59 %r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
60 ret {float, float, float, float, float} %r4
71 …float @ps_input_ena_no_inputs([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>…
72 ret float 1.0
85 …float, <2 x float>} @ps_input_ena_pos_w([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg,…
86 %f = bitcast <2 x i32> %8 to <2 x float>
87 %s = insertvalue {float, <2 x float>} undef, float %14, 0
88 %s1 = insertvalue {float, <2 x float>} %s, <2 x float> %f, 1
89 ret {float, <2 x float>} %s1
105 …float, float, float, float, float} @vgpr_ps_addr1([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, …
110 %f0 = bitcast i32 %i0 to float
111 %f1 = bitcast i32 %i1 to float
112 %f2 = bitcast i32 %i2 to float
113 %f3 = bitcast i32 %i3 to float
114 %r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
115 %r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
116 %r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
117 %r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
118 %r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
119 ret {float, float, float, float, float} %r4
135 …float, float, float, float, float} @vgpr_ps_addr119([9 x <16 x i8>] addrspace(2)* byval, i32 inreg…
140 %f0 = bitcast i32 %i0 to float
141 %f1 = bitcast i32 %i1 to float
142 %f2 = bitcast i32 %i2 to float
143 %f3 = bitcast i32 %i3 to float
144 %r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
145 %r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
146 %r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
147 %r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
148 %r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
149 ret {float, float, float, float, float} %r4
165 …float, float, float, float, float} @vgpr_ps_addr418([9 x <16 x i8>] addrspace(2)* byval, i32 inreg…
170 %f0 = bitcast i32 %i0 to float
171 %f1 = bitcast i32 %i1 to float
172 %f2 = bitcast i32 %i2 to float
173 %f3 = bitcast i32 %i3 to float
174 %r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
175 %r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
176 %r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
177 %r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
178 %r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
179 ret {float, float, float, float, float} %r4
187 …amdgpu_vs {i32, i32, i32} @sgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) {
203 …2, i32, i32, i32} @sgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) {
218 define amdgpu_vs {float, i32, float, i32, i32} @both([9 x <16 x i8>] addrspace(2)* byval, i32 inreg…
219 …call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float …
220 %v = fadd float %3, 1.0
222 %a0 = insertvalue {float, i32, float, i32, i32} undef, float %v, 0
223 %a1 = insertvalue {float, i32, float, i32, i32} %a0, i32 %s, 1
224 %a2 = insertvalue {float, i32, float, i32, i32} %a1, float %3, 2
225 %a3 = insertvalue {float, i32, float, i32, i32} %a2, i32 %1, 3
226 %a4 = insertvalue {float, i32, float, i32, i32} %a3, i32 %2, 4
227 ret {float, i32, float, i32, i32} %a4
239 …efine amdgpu_vs {{float, i32}, {i32, <2 x float>}} @structure_literal([9 x <16 x i8>] addrspace(2)…
240 …call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float …
241 …ret {{float, i32}, {i32, <2 x float>}} {{float, i32} {float 1.0, i32 2}, {i32, <2 x float>} {i32 3…