Lines Matching refs:SI

1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
7 ; SI-LABEL: {{^}}trunc_i64_to_i32_store:
8 ; SI: s_load_dword [[SLOAD:s[0-9]+]], s[0:1], 0xb
9 ; SI: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
10 ; SI: buffer_store_dword [[VLOAD]]
21 ; SI-LABEL: {{^}}trunc_load_shl_i64:
22 ; SI-DAG: s_load_dwordx2
23 ; SI-DAG: s_load_dword [[SREG:s[0-9]+]],
24 ; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
25 ; SI: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
26 ; SI: buffer_store_dword [[VSHL]],
34 ; SI-LABEL: {{^}}trunc_shl_i64:
35 ; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
36 ; SI: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
37 ; SI: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
38 ; SI: s_addc_u32
39 ; SI: v_mov_b32_e32
40 ; SI: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
41 ; SI: v_mov_b32_e32
42 ; SI: buffer_store_dword v[[LO_VREG]],
52 ; SI-LABEL: {{^}}trunc_i32_to_i1:
53 ; SI: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
54 ; SI: v_cmp_eq_i32
63 ; SI-LABEL: {{^}}sgpr_trunc_i32_to_i1:
64 ; SI: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}
65 ; SI: v_cmp_eq_i32
73 ; SI-LABEL: {{^}}s_trunc_i64_to_i1:
74 ; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb
75 ; SI: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]
76 ; SI: v_cmp_eq_i32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], 1, [[MASKED]]
77 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]
85 ; SI-LABEL: {{^}}v_trunc_i64_to_i1:
86 ; SI: buffer_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
87 ; SI: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
88 ; SI: v_cmp_eq_i32_e32 vcc, 1, [[MASKED]]
89 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc