Lines Matching refs:vcc

34 ; SI-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
35 ; SI-DAG: s_and_b64 vcc, exec, [[COND]]
91 ; SI-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
92 ; SI-DAG: s_and_b64 vcc, exec, [[COND]]
122 ; SI: v_cmp_ne_i32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 5, [[CMP]]
123 ; SI: s_and_b64 vcc, exec, [[COND]]
147 ; SI: v_cmp_gt_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 6, [[CMP]]
148 ; SI: s_and_b64 vcc, exec, [[COND]]
257 ; SI: s_and_b64 vcc, exec, [[MASK]]
286 ; SI: v_add_i32_e32 [[I:v[0-9]+]], vcc, -1, v{{[0-9]+}}
287 ; SI: v_cmp_ne_i32_e32 vcc, 0, [[I]]
288 ; SI: s_and_b64 vcc, exec, vcc
308 ; SI: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
309 ; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
338 ; SI: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
339 ; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
365 ; SI: v_cmp_eq_i32_e32 vcc, 0, v0
366 ; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc