Lines Matching refs:REG

5 ; CHECK:      vld1.16   {[[REG:d[0-9]+]][0]}, [r0:16]
6 ; CHECK-NEXT: vrev16.8  [[REG]], [[REG]]
7 ; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
8 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
9 ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
10 ; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
20 ; CHECK:      vld1.32   {[[REG:d[0-9]+]][0]}, [r0:32]
21 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
22 ; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
23 ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
24 ; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
35 ; CHECK:      vld1.16   {[[REG:d[0-9]+]][0]}, [r0:16]
36 ; CHECK-NEXT: vrev16.8  [[REG]], [[REG]]
37 ; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
38 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
39 ; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
40 ; CHECK-NEXT: vstr      [[REG]], [r1]
50 ; CHECK:      vld1.32   {[[REG:d[0-9]+]][0]}, [r0:32]
51 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
52 ; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
53 ; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
54 ; CHECK-NEXT: vstr      [[REG]], [r1]
64 ; CHECK:      vld1.16   {[[REG:d[0-9]+]][0]}, [r0:16]
65 ; CHECK-NEXT: vrev16.8  [[REG]], [[REG]]
66 ; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
67 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
68 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
69 ; CHECK-NEXT: vuzp.16   [[REG]], {{d[0-9]+}}
70 ; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
71 ; CHECK-NEXT: vst1.32   {[[REG]][0]}, [r1:32]
81 ; CHECK:      vld1.32   {[[REG:d[0-9]+]][0]}, [r0:32]
82 ; CHECK-NEXT: vrev32.8  [[REG]], [[REG]]
83 ; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
84 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
86 ; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
96 ; CHECK:      vld1.32   {[[REG:d[0-9]+]][0]}, [r0:32]
97 ; CHECK-NEXT: vrev32.8  [[REG]], [[REG]]
98 ; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
99 ; CHECK-NEXT: vrev64.16 [[REG]], [[REG]]
100 ; CHECK-NEXT: vstr      [[REG]], [r1]