Lines Matching refs:coerce

37 define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
39   %0 = bitcast i32 %a.coerce to <2 x i16>
40   %1 = bitcast i32 %b.coerce to <2 x i16>
50 define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
52   %0 = bitcast i32 %a.coerce to <2 x i16>
53   %1 = bitcast i32 %b.coerce to <2 x i16>
68 define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) {
70   %0 = bitcast i32 %a.coerce to <2 x i16>
71   %1 = bitcast i32 %b.coerce to <2 x i16>
81 define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
83   %0 = bitcast i32 %a.coerce to <4 x i8>
84   %1 = bitcast i32 %b.coerce to <4 x i8>
94 define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) {
96   %0 = bitcast i32 %a.coerce to <4 x i8>
97   %1 = bitcast i32 %b.coerce to <4 x i8>
111 define { i32 } @test_mul_v4i8_(i32 %a.coerce, i32 %b.coerce) {
113   %0 = bitcast i32 %a.coerce to <4 x i8>
114   %1 = bitcast i32 %b.coerce to <4 x i8>
134 define { i32 } @shift1_v2i16_shl_(i32 %a0.coerce) {
136   %0 = bitcast i32 %a0.coerce to <2 x i16>
146 define { i32 } @shift1_v2i16_sra_(i32 %a0.coerce) {
148   %0 = bitcast i32 %a0.coerce to <2 x i16>
160 define { i32 } @shift1_v2ui16_srl_(i32 %a0.coerce) {
162   %0 = bitcast i32 %a0.coerce to <2 x i16>
172 define { i32 } @shift1_v4i8_shl_(i32 %a0.coerce) {
174   %0 = bitcast i32 %a0.coerce to <4 x i8>
186 define { i32 } @shift1_v4i8_sra_(i32 %a0.coerce) {
188   %0 = bitcast i32 %a0.coerce to <4 x i8>
198 define { i32 } @shift1_v4ui8_srl_(i32 %a0.coerce) {
200   %0 = bitcast i32 %a0.coerce to <4 x i8>
212 define { i32 } @test_vector_splat_imm_v2q15(i32 %a.coerce) {
214   %0 = bitcast i32 %a.coerce to <2 x i16>
226 define { i32 } @test_vector_splat_imm_v4i8(i32 %a.coerce) {
228   %0 = bitcast i32 %a.coerce to <4 x i8>
240 define { i32 } @test_shift_amount_v2q15(i32 %a.coerce) {
242   %0 = bitcast i32 %a.coerce to <2 x i16>
254 define { i32 } @test_shift_amount_v4i8(i32 %a.coerce) {
256   %0 = bitcast i32 %a.coerce to <4 x i8>