Lines Matching full:32

1 ; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,32-NOFPXX
2 ; RUN: llc -march=mipsel -mcpu=mips32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32-FPXX
4 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,32R2-NOFPXX
5 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32R2-FP…
29 ; 32-NOFPXX:     mtc1    $4, $f0
30 ; 32-NOFPXX:     mtc1    $5, $f1
32 ; 32-FPXX:       addiu   $sp, $sp, -8
33 ; 32-FPXX:       sw      $4, 0($sp)
34 ; 32-FPXX:       sw      $5, 4($sp)
35 ; 32-FPXX:       ldc1    $f0, 0($sp)
37 ; 32R2-NOFPXX:   mtc1    $4, $f0
38 ; 32R2-NOFPXX:   mthc1   $5, $f0
40 ; 32R2-FPXX:     mtc1    $4, $f0
41 ; 32R2-FPXX:     mthc1   $5, $f0
54 ; 32-NOFPXX:     mtc1    $6, $f0
55 ; 32-NOFPXX:     mtc1    $7, $f1
57 ; 32-FPXX:       addiu   $sp, $sp, -8
58 ; 32-FPXX:       sw      $6, 0($sp)
59 ; 32-FPXX:       sw      $7, 4($sp)
60 ; 32-FPXX:       ldc1    $f0, 0($sp)
62 ; 32R2-NOFPXX:   mtc1    $6, $f0
63 ; 32R2-NOFPXX:   mthc1   $7, $f0
65 ; 32R2-FPXX:     mtc1    $6, $f0
66 ; 32R2-FPXX:     mthc1   $7, $f0
78 ; 32-NOFPXX:     mtc1    $6, $f0
79 ; 32-NOFPXX:     mtc1    $7, $f1
81 ; 32-FPXX:       addiu   $sp, $sp, -8
82 ; 32-FPXX:       sw      $6, 0($sp)
83 ; 32-FPXX:       sw      $7, 4($sp)
84 ; 32-FPXX:       ldc1    $f0, 0($sp)
86 ; 32R2-NOFPXX:   mtc1    $6, $f0
87 ; 32R2-NOFPXX:   mthc1   $7, $f0
89 ; 32R2-FPXX:     mtc1    $6, $f0
90 ; 32R2-FPXX:     mthc1   $7, $f0
102 ; 32-NOFPXX:     mtc1    $6, $f0
103 ; 32-NOFPXX:     mtc1    $7, $f1
105 ; 32-FPXX:       addiu   $sp, $sp, -8
106 ; 32-FPXX:       sw      $6, 0($sp)
107 ; 32-FPXX:       sw      $7, 4($sp)
108 ; 32-FPXX:       ldc1    $f0, 0($sp)
110 ; 32R2-NOFPXX:   mtc1    $6, $f0
111 ; 32R2-NOFPXX:   mthc1   $7, $f0
113 ; 32R2-FPXX:     mtc1    $6, $f0
114 ; 32R2-FPXX:     mthc1   $7, $f0
126 ; 32-NOFPXX:     mtc1    $zero, $f0
127 ; 32-NOFPXX:     mtc1    $zero, $f1
129 ; 32-FPXX:       addiu   $sp, $sp, -8
130 ; 32-FPXX:       sw      $zero, 0($sp)
131 ; 32-FPXX:       sw      $zero, 4($sp)
132 ; 32-FPXX:       ldc1    $f0, 0($sp)
134 ; 32R2-NOFPXX:   mtc1    $zero, $f0
135 ; 32R2-NOFPXX:   mthc1   $zero, $f0
137 ; 32R2-FPXX:     mtc1    $zero, $f0
138 ; 32R2-FPXX:     mthc1   $zero, $f0
151 ; 32-NOFPXX-DAG:     mtc1    $4, $[[T0:f[0-9]+]]
152 ; 32-NOFPXX-DAG:     mtc1    $5, ${{f[0-9]*[13579]}}
153 ; 32-NOFPXX-DAG:     mtc1    $6, $[[T1:f[0-9]+]]
154 ; 32-NOFPXX-DAG:     mtc1    $7, ${{f[0-9]*[13579]}}
155 ; 32-NOFPXX:         sub.d   $f0, $[[T0]], $[[T1]]
157 ; 32-FPXX:           addiu   $sp, $sp, -8
158 ; 32-FPXX:           sw      $6, 0($sp)
159 ; 32-FPXX:           sw      $7, 4($sp)
160 ; 32-FPXX:           ldc1    $[[T1:f[0-9]+]], 0($sp)
161 ; 32-FPXX:           sw      $4, 0($sp)
162 ; 32-FPXX:           sw      $5, 4($sp)
163 ; 32-FPXX:           ldc1    $[[T0:f[0-9]+]], 0($sp)
164 ; 32-FPXX:           sub.d   $f0, $[[T0]], $[[T1]]
166 ; 32R2-NOFPXX-DAG:   mtc1    $4, $[[T0:f[0-9]+]]
167 ; 32R2-NOFPXX-DAG:   mthc1   $5, $[[T0]]
168 ; 32R2-NOFPXX-DAG:   mtc1    $6, $[[T1:f[0-9]+]]
169 ; 32R2-NOFPXX-DAG:   mthc1   $7, $[[T1]]
170 ; 32R2-NOFPXX:       sub.d   $f0, $[[T0]], $[[T1]]
172 ; 32R2-FPXX-DAG:     mtc1    $4, $[[T0:f[0-9]+]]
173 ; 32R2-FPXX-DAG:     mthc1   $5, $[[T0]]
174 ; 32R2-FPXX-DAG:     mtc1    $6, $[[T1:f[0-9]+]]
175 ; 32R2-FPXX-DAG:     mthc1   $7, $[[T1]]
176 ; 32R2-FPXX:         sub.d   $f0, $[[T0]], $[[T1]]
192 ; 32-NOFPXX-DAG:   mfc1    $6, $f0
193 ; 32-NOFPXX-DAG:   mfc1    $7, $f1
195 ; 32-FPXX:         addiu   $sp, $sp, -32
196 ; 32-FPXX:         sdc1    $f0, 16($sp)
197 ; 32-FPXX:         lw      $6, 16($sp)
199 ; 32-FPXX:         sdc1    $f0, 16($sp)
200 ; 32-FPXX:         lw      $7, 20($sp)
202 ; 32R2-NOFPXX-DAG: mfc1    $6, $f0
203 ; 32R2-NOFPXX-DAG: mfhc1   $7, $f0
205 ; 32R2-FPXX-DAG:   mfc1    $6, $f0
206 ; 32R2-FPXX-DAG:   mfhc1   $7, $f0