Lines Matching refs:InVec
6 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
11 …%shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 …
15 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
21 …%shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
25 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
31 …%shl = shl <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16…
35 define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
40 %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
44 define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
50 %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
66 define <8 x i32> @test_slld_3(<8 x i32> %InVec) {
72 %shl = shl <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
76 define <4 x i64> @test_sllq_1(<4 x i64> %InVec) {
81 %shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
85 define <4 x i64> @test_sllq_2(<4 x i64> %InVec) {
91 %shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
95 define <4 x i64> @test_sllq_3(<4 x i64> %InVec) {
101 %shl = shl <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>
107 define <16 x i16> @test_sraw_1(<16 x i16> %InVec) {
112 …%shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16…
116 define <16 x i16> @test_sraw_2(<16 x i16> %InVec) {
122 …%shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16…
126 define <16 x i16> @test_sraw_3(<16 x i16> %InVec) {
132 …%shl = ashr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i1…
136 define <8 x i32> @test_srad_1(<8 x i32> %InVec) {
141 %shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
145 define <8 x i32> @test_srad_2(<8 x i32> %InVec) {
151 %shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
155 define <8 x i32> @test_srad_3(<8 x i32> %InVec) {
161 %shl = ashr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
167 define <16 x i16> @test_srlw_1(<16 x i16> %InVec) {
172 …%shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16…
176 define <16 x i16> @test_srlw_2(<16 x i16> %InVec) {
182 …%shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16…
186 define <16 x i16> @test_srlw_3(<16 x i16> %InVec) {
192 …%shl = lshr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i1…
196 define <8 x i32> @test_srld_1(<8 x i32> %InVec) {
201 %shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
205 define <8 x i32> @test_srld_2(<8 x i32> %InVec) {
211 %shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
215 define <8 x i32> @test_srld_3(<8 x i32> %InVec) {
221 %shl = lshr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
225 define <4 x i64> @test_srlq_1(<4 x i64> %InVec) {
230 %shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
234 define <4 x i64> @test_srlq_2(<4 x i64> %InVec) {
240 %shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
244 define <4 x i64> @test_srlq_3(<4 x i64> %InVec) {
250 %shl = lshr <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>