Lines Matching refs:msr

117 # CHECK: msr      {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27
119 # CHECK: msr      {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5
121 # CHECK: msr      {{icc_dir_el1|ICC_DIR_EL1}}, x13
123 # CHECK: msr      {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21
125 # CHECK: msr      {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25
127 # CHECK: msr      {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28
129 # CHECK: msr      {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7
131 # CHECK: msr      {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9
133 # CHECK: msr      {{icc_pmr_el1|ICC_PMR_EL1}}, x29
135 # CHECK: msr      {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24
137 # CHECK: msr      {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0
139 # CHECK: msr      {{icc_sre_el1|ICC_SRE_EL1}}, x2
141 # CHECK: msr      {{icc_sre_el2|ICC_SRE_EL2}}, x5
143 # CHECK: msr      {{icc_sre_el3|ICC_SRE_EL3}}, x10
145 # CHECK: msr      {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22
147 # CHECK: msr      {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11
149 # CHECK: msr      {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8
151 # CHECK: msr      {{icc_seien_el1|ICC_SEIEN_EL1}}, x4
153 # CHECK: msr      {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27
155 # CHECK: msr      {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5
157 # CHECK: msr      {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20
159 # CHECK: msr      {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0
161 # CHECK: msr      {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2
163 # CHECK: msr      {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29
165 # CHECK: msr      {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23
167 # CHECK: msr      {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11
169 # CHECK: msr      {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2
171 # CHECK: msr      {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27
173 # CHECK: msr      {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7
175 # CHECK: msr      {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1
177 # CHECK: msr      {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7
179 # CHECK: msr      {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12
181 # CHECK: msr      {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14
183 # CHECK: msr      {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13
185 # CHECK: msr      {{ich_hcr_el2|ICH_HCR_EL2}}, x1
187 # CHECK: msr      {{ich_misr_el2|ICH_MISR_EL2}}, x10
189 # CHECK: msr      {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24
191 # CHECK: msr      {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29
193 # CHECK: msr      {{ich_lr0_el2|ICH_LR0_EL2}}, x26
195 # CHECK: msr      {{ich_lr1_el2|ICH_LR1_EL2}}, x9
197 # CHECK: msr      {{ich_lr2_el2|ICH_LR2_EL2}}, x18
199 # CHECK: msr      {{ich_lr3_el2|ICH_LR3_EL2}}, x26
201 # CHECK: msr      {{ich_lr4_el2|ICH_LR4_EL2}}, x22
203 # CHECK: msr      {{ich_lr5_el2|ICH_LR5_EL2}}, x26
205 # CHECK: msr      {{ich_lr6_el2|ICH_LR6_EL2}}, x27
207 # CHECK: msr      {{ich_lr7_el2|ICH_LR7_EL2}}, x8
209 # CHECK: msr      {{ich_lr8_el2|ICH_LR8_EL2}}, x17
211 # CHECK: msr      {{ich_lr9_el2|ICH_LR9_EL2}}, x19
213 # CHECK: msr      {{ich_lr10_el2|ICH_LR10_EL2}}, x17
215 # CHECK: msr      {{ich_lr11_el2|ICH_LR11_EL2}}, x5
217 # CHECK: msr      {{ich_lr12_el2|ICH_LR12_EL2}}, x29
219 # CHECK: msr      {{ich_lr13_el2|ICH_LR13_EL2}}, x2
221 # CHECK: msr      {{ich_lr14_el2|ICH_LR14_EL2}}, x13
223 # CHECK: msr      {{ich_lr15_el2|ICH_LR15_EL2}}, x27