Lines Matching refs:RecVec
139 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor"); in collectProcModels()
179 static void scanSchedRW(Record *RWDef, RecVec &RWDefs, in scanSchedRW()
186 RecVec Seq = RWDef->getValueAsListOfDefs("Writes"); in scanSchedRW()
192 RecVec Vars = RWDef->getValueAsListOfDefs("Variants"); in scanSchedRW()
195 RecVec Selected = (*VI)->getValueAsListOfDefs("Selected"); in scanSchedRW()
212 RecVec SWDefs, SRDefs; in collectSchedRW()
217 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW"); in collectSchedRW()
228 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW"); in collectSchedRW()
231 RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()
243 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW"); in collectSchedRW()
246 RecVec RWDefs = (*II)->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()
259 RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias"); in collectSchedRW()
317 RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite"); in collectSchedRW()
358 RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites"); in hasReadOfWrite()
368 void splitSchedReadWrites(const RecVec &RWDefs, in splitSchedReadWrites()
369 RecVec &WriteDefs, RecVec &ReadDefs) { in splitSchedReadWrites()
382 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, in findRWs()
384 RecVec WriteDefs; in findRWs()
385 RecVec ReadDefs; in findRWs()
392 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs, in findRWs()
520 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW"); in collectSchedClasses()
560 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs; in collectSchedClasses()
627 std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) { in createSchedClassName()
679 const RecVec *InstDefs = Sets.expand(InstRWDef); in createInstRWClass()
708 const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs; in createInstRWClass()
710 const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]); in createInstRWClass()
782 RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID"); in collectProcItins()
821 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW"); in collectProcItinRW()
876 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses"); in inferFromItinClass()
897 const RecVec *InstDefs = Sets.expand(Rec); in inferFromInstRWs()
993 RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants"); in mutuallyExclusive()
1071 const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants"); in getIntersectingVariants()
1091 const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants"); in getIntersectingVariants()
1160 RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected"); in pushVariant()
1321 RecVec Preds; in inferFromTransitions()
1395 bool CodeGenSchedModels::hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM) { in hasSuperGroup()
1399 RecVec SuperUnits = in hasSuperGroup()
1419 RecVec CheckUnits = in verifyProcResourceGroups()
1424 RecVec OtherUnits = in verifyProcResourceGroups()
1473 RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes"); in collectProcResources()
1478 RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes"); in collectProcResources()
1483 RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance"); in collectProcResources()
1488 RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance"); in collectProcResources()
1497 RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup"); in collectProcResources()
1574 const RecVec &InstRWs = SC.InstRWs; in checkCompleteness()
1609 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses"); in collectItinProcResources()
1743 RecVec &WRDefs = ProcModels[PIdx].WriteResDefs; in addWriteRes()
1750 RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources"); in addWriteRes()
1760 RecVec &RADefs = ProcModels[PIdx].ReadAdvanceDefs; in addReadAdvance()