Lines Matching refs:BOOL_32

555     BOOL_32         last2DLevel;    ///< TRUE if this is the last 2D(3D) tiled
600     BOOL_32         isDepth;            ///< TRUE if the surface uses depth sample ordering within
634     BOOL_32         is32ByteTile;       ///< Caller must have access to HTILE buffer and know if
694     BOOL_32         isDepth;            ///< Surface uses depth sample ordering within micro tile.
797     BOOL_32            isLinear;        ///< Linear or tiled HTILE layout
865     BOOL_32            isLinear;        ///< Linear or tiled HTILE layout
926     BOOL_32            isLinear;        ///< Linear or tiled HTILE layout
1009     BOOL_32             isLinear;        ///< Linear or tiled layout, Only SI can be linear
1079     BOOL_32          isLinear;       ///< Linear or tiled layout, Only SI can be linear
1139     BOOL_32        isLinear;        ///< Linear or tiled layout, Only SI can be linear
1438 BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib);
1448 BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib);
1751 BOOL_32 ADDR_API ElemGetExportNorm(
1881     BOOL_32         reverse;            ///< Convert control flag.
1940     BOOL_32         tileInfoHw;         ///< Set to TRUE if client wants HW enum, otherwise actual
1991     BOOL_32         tileInfoHw;         ///< Set to TRUE if client wants HW enum, otherwise actual
2143     BOOL_32 subLvlCompressible;   ///< whether sub resource is compressiable