Lines Matching refs:pTileInfo
96 ADDR_TILEINFO* pTileInfo = &tileInfoDef; in DispatchComputeSurfaceInfo() local
117 ADDR_ASSERT(pOut->pTileInfo); in DispatchComputeSurfaceInfo()
119 if (pOut->pTileInfo != NULL) in DispatchComputeSurfaceInfo()
121 pTileInfo = pOut->pTileInfo; in DispatchComputeSurfaceInfo()
125 if (pIn->pTileInfo != NULL) in DispatchComputeSurfaceInfo()
127 if (pTileInfo != pIn->pTileInfo) in DispatchComputeSurfaceInfo()
129 *pTileInfo = *pIn->pTileInfo; in DispatchComputeSurfaceInfo()
134 memset(pTileInfo, 0, sizeof(ADDR_TILEINFO)); in DispatchComputeSurfaceInfo()
144 pIn->pTileInfo, in DispatchComputeSurfaceInfo()
145 pTileInfo, in DispatchComputeSurfaceInfo()
258 pOut->pTileInfo, in ComputeSurfaceInfoLinear()
372 pOut->pTileInfo, in ComputeSurfaceInfoMicroTiled()
448 pOut->pTileInfo, in ComputeSurfaceInfoMacroTiled()
476 pOut->pTileInfo); in ComputeSurfaceInfoMacroTiled()
507 pOut->pTileInfo, in ComputeSurfaceInfoMacroTiled()
520 pOut->pTileInfo, in ComputeSurfaceInfoMacroTiled()
535 UINT_32 checkMask = pOut->pTileInfo->banks - 1; in ComputeSurfaceInfoMacroTiled()
539 bankBits = (paddedHeight / 8 / pOut->pTileInfo->bankHeight) & checkMask; in ComputeSurfaceInfoMacroTiled()
704 ADDR_TILEINFO* pTileInfo ///< [in/out] bank structure. in HwlReduceBankWidthHeight()
710 if (tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize) in HwlReduceBankWidthHeight()
715 if (stillGreater && pTileInfo->bankWidth > 1) in HwlReduceBankWidthHeight()
717 while (stillGreater && pTileInfo->bankWidth > 0) in HwlReduceBankWidthHeight()
719 pTileInfo->bankWidth >>= 1; in HwlReduceBankWidthHeight()
721 if (pTileInfo->bankWidth == 0) in HwlReduceBankWidthHeight()
723 pTileInfo->bankWidth = 1; in HwlReduceBankWidthHeight()
728 tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize; in HwlReduceBankWidthHeight()
734 (tileSize * pTileInfo->bankWidth) in HwlReduceBankWidthHeight()
738 ADDR_ASSERT((pTileInfo->bankHeight % bankHeightAlign) == 0); in HwlReduceBankWidthHeight()
744 (tileSize * pipes * pTileInfo->bankWidth) in HwlReduceBankWidthHeight()
746 pTileInfo->macroAspectRatio = PowTwoAlign(pTileInfo->macroAspectRatio, in HwlReduceBankWidthHeight()
758 if (stillGreater && pTileInfo->bankHeight > bankHeightAlign) in HwlReduceBankWidthHeight()
760 while (stillGreater && pTileInfo->bankHeight > bankHeightAlign) in HwlReduceBankWidthHeight()
762 pTileInfo->bankHeight >>= 1; in HwlReduceBankWidthHeight()
764 if (pTileInfo->bankHeight < bankHeightAlign) in HwlReduceBankWidthHeight()
766 pTileInfo->bankHeight = bankHeightAlign; in HwlReduceBankWidthHeight()
771 tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize; in HwlReduceBankWidthHeight()
782 tileSize, pTileInfo->bankWidth, pTileInfo->bankHeight, m_rowSize)); in HwlReduceBankWidthHeight()
807 ADDR_TILEINFO* pTileInfo, ///< [in/out] bank structure. in ComputeSurfaceAlignmentsMacroTiled() argument
813 BOOL_32 valid = SanityCheckMacroTiled(pTileInfo); in ComputeSurfaceAlignmentsMacroTiled()
825 UINT_32 pipes = HwlGetPipes(pTileInfo); in ComputeSurfaceAlignmentsMacroTiled()
832 tileSize = Min(pTileInfo->tileSplitBytes, in ComputeSurfaceAlignmentsMacroTiled()
839 (tileSize * pTileInfo->bankWidth) in ComputeSurfaceAlignmentsMacroTiled()
842 pTileInfo->bankHeight = PowTwoAlign(pTileInfo->bankHeight, bankHeightAlign); in ComputeSurfaceAlignmentsMacroTiled()
851 (tileSize * pipes * pTileInfo->bankWidth) in ComputeSurfaceAlignmentsMacroTiled()
853 … pTileInfo->macroAspectRatio = PowTwoAlign(pTileInfo->macroAspectRatio, macroAspectAlign); in ComputeSurfaceAlignmentsMacroTiled()
862 pTileInfo); in ComputeSurfaceAlignmentsMacroTiled()
867 macroTileWidth = MicroTileWidth * pTileInfo->bankWidth * pipes * in ComputeSurfaceAlignmentsMacroTiled()
868 pTileInfo->macroAspectRatio; in ComputeSurfaceAlignmentsMacroTiled()
877 macroTileHeight = MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks / in ComputeSurfaceAlignmentsMacroTiled()
878 pTileInfo->macroAspectRatio; in ComputeSurfaceAlignmentsMacroTiled()
886 pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight * tileSize; in ComputeSurfaceAlignmentsMacroTiled()
920 ADDR_TILEINFO* pTileInfo ///< [in] macro-tiled parameters in SanityCheckMacroTiled()
924 UINT_32 numPipes = HwlGetPipes(pTileInfo); in SanityCheckMacroTiled()
926 switch (pTileInfo->banks) in SanityCheckMacroTiled()
941 switch (pTileInfo->bankWidth) in SanityCheckMacroTiled()
956 switch (pTileInfo->bankHeight) in SanityCheckMacroTiled()
971 switch (pTileInfo->macroAspectRatio) in SanityCheckMacroTiled()
986 if (pTileInfo->banks < pTileInfo->macroAspectRatio) in SanityCheckMacroTiled()
995 if (pTileInfo->tileSplitBytes > m_rowSize) in SanityCheckMacroTiled()
1003 valid = HwlSanityCheckMacroTiled(pTileInfo); in SanityCheckMacroTiled()
1009 ADDR_ASSERT(numPipes * pTileInfo->banks >= 4); in SanityCheckMacroTiled()
1034 ADDR_TILEINFO* pTileInfo ///< [in] ptr to bank structure in ComputeSurfaceMipLevelTileMode()
1057 if (bytesPerTile > pTileInfo->tileSplitBytes) in ComputeSurfaceMipLevelTileMode()
1059 bytesPerTile = pTileInfo->tileSplitBytes; in ComputeSurfaceMipLevelTileMode()
1063 bytesPerTile * HwlGetPipes(pTileInfo) * pTileInfo->bankWidth * pTileInfo->macroAspectRatio; in ComputeSurfaceMipLevelTileMode()
1066 bytesPerTile * pTileInfo->bankWidth * pTileInfo->bankHeight; in ComputeSurfaceMipLevelTileMode()
1127 ADDR_ASSERT(pIn->pTileInfo); in HwlDegradeBaseLevel()
1128 ADDR_TILEINFO tileInfo = *pIn->pTileInfo; in HwlDegradeBaseLevel()
1273 ADDR_TILEINFO* pTileInfo = pIn->pTileInfo; in DispatchComputeSurfaceAddrFromCoord() local
1356 ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo, in DispatchComputeSurfaceAddrFromCoord()
1379 pTileInfo, in DispatchComputeSurfaceAddrFromCoord()
1434 ADDR_TILEINFO* pTileInfo, ///< [in] bank structure in ComputeSurfaceAddrFromCoordMacroTiled() argument
1476 UINT_32 numPipes = HwlGetPipes(pTileInfo); in ComputeSurfaceAddrFromCoordMacroTiled()
1480 UINT_32 numBankBits = Log2(pTileInfo->banks); in ComputeSurfaceAddrFromCoordMacroTiled()
1538 if ((microTileBytes > pTileInfo->tileSplitBytes) && (microTileThickness == 1)) in ComputeSurfaceAddrFromCoordMacroTiled()
1544 slicesPerTile = microTileBytes / pTileInfo->tileSplitBytes; in ComputeSurfaceAddrFromCoordMacroTiled()
1549 tileSplitSlice = elementOffset / pTileInfo->tileSplitBytes; in ComputeSurfaceAddrFromCoordMacroTiled()
1555 elementOffset %= pTileInfo->tileSplitBytes; in ComputeSurfaceAddrFromCoordMacroTiled()
1561 microTileBytes = pTileInfo->tileSplitBytes; in ComputeSurfaceAddrFromCoordMacroTiled()
1572 (MicroTileWidth * pTileInfo->bankWidth * numPipes) * pTileInfo->macroAspectRatio; in ComputeSurfaceAddrFromCoordMacroTiled()
1574 (MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks) / pTileInfo->macroAspectRatio; in ComputeSurfaceAddrFromCoordMacroTiled()
1582 (numPipes * pTileInfo->banks); in ComputeSurfaceAddrFromCoordMacroTiled()
1614 tileRowIndex = (y / MicroTileHeight) % pTileInfo->bankHeight; in ComputeSurfaceAddrFromCoordMacroTiled()
1615 tileColumnIndex = ((x / MicroTileWidth) / numPipes) % pTileInfo->bankWidth; in ComputeSurfaceAddrFromCoordMacroTiled()
1616 tileIndex = (tileRowIndex * pTileInfo->bankWidth) + tileColumnIndex; in ComputeSurfaceAddrFromCoordMacroTiled()
1642 pTileInfo); in ComputeSurfaceAddrFromCoordMacroTiled()
1650 pTileInfo); in ComputeSurfaceAddrFromCoordMacroTiled()
2026 ADDR_TILEINFO* pTileInfo = pIn->pTileInfo; in DispatchComputeSurfaceCoordFromAddr() local
2107 ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo, in DispatchComputeSurfaceCoordFromAddr()
2130 pTileInfo, in DispatchComputeSurfaceCoordFromAddr()
2167 ADDR_TILEINFO* pTileInfo, ///< [in] bank structure. in ComputeSurfaceCoordFromAddrMacroTiled() argument
2190 UINT_32 pipes = HwlGetPipes(pTileInfo); in ComputeSurfaceCoordFromAddrMacroTiled()
2191 UINT_32 banks = pTileInfo->banks; in ComputeSurfaceCoordFromAddrMacroTiled()
2217 if ((microTileBytes > pTileInfo->tileSplitBytes) && (microTileThickness == 1)) in ComputeSurfaceCoordFromAddrMacroTiled()
2223 slicesPerTile = microTileBytes / pTileInfo->tileSplitBytes; in ComputeSurfaceCoordFromAddrMacroTiled()
2229 UINT_32 macroWidth = pTileInfo->bankWidth * pipes * pTileInfo->macroAspectRatio; in ComputeSurfaceCoordFromAddrMacroTiled()
2231 UINT_32 macroHeight = pTileInfo->bankHeight * banks / pTileInfo->macroAspectRatio; in ComputeSurfaceCoordFromAddrMacroTiled()
2278 my = (tileIndex / pTileInfo->bankWidth) % pTileInfo->bankHeight * MicroTileHeight; in ComputeSurfaceCoordFromAddrMacroTiled()
2279 mx = (tileIndex % pTileInfo->bankWidth) * pipes * MicroTileWidth; in ComputeSurfaceCoordFromAddrMacroTiled()
2297 pTileInfo); in ComputeSurfaceCoordFromAddrMacroTiled()
2320 ADDR_TILEINFO* pTileInfo, ///< [in] bank structure. **All fields to be valid on entry** in ComputeSurfaceCoord2DFromBankPipe() argument
2335 UINT_32 numPipes = HwlGetPipes(pTileInfo); in ComputeSurfaceCoord2DFromBankPipe()
2338 pTileInfo->banks, numPipes); in ComputeSurfaceCoord2DFromBankPipe()
2342 UINT_32 xBit = x / (MicroTileWidth * pTileInfo->bankWidth * numPipes); in ComputeSurfaceCoord2DFromBankPipe()
2343 UINT_32 yBit = y / (MicroTileHeight * pTileInfo->bankHeight); in ComputeSurfaceCoord2DFromBankPipe()
2355 tileSplitRotation = ((pTileInfo->banks / 2) + 1); in ComputeSurfaceCoord2DFromBankPipe()
2368 bank %= pTileInfo->banks; in ComputeSurfaceCoord2DFromBankPipe()
2374 bank %= pTileInfo->banks; in ComputeSurfaceCoord2DFromBankPipe()
2378 if (pTileInfo->macroAspectRatio == 1) in ComputeSurfaceCoord2DFromBankPipe()
2380 switch (pTileInfo->banks) in ComputeSurfaceCoord2DFromBankPipe()
2405 else if (pTileInfo->macroAspectRatio == 2) in ComputeSurfaceCoord2DFromBankPipe()
2407 switch (pTileInfo->banks) in ComputeSurfaceCoord2DFromBankPipe()
2431 else if (pTileInfo->macroAspectRatio == 4) in ComputeSurfaceCoord2DFromBankPipe()
2433 switch (pTileInfo->banks) in ComputeSurfaceCoord2DFromBankPipe()
2454 else if (pTileInfo->macroAspectRatio == 8) in ComputeSurfaceCoord2DFromBankPipe()
2456 switch (pTileInfo->banks) in ComputeSurfaceCoord2DFromBankPipe()
2501 pIn->pTileInfo, in HwlExtractBankPipeSwizzle()
2521 ADDR_TILEINFO* pTileInfo, ///< [in] tile info in HwlCombineBankPipeSwizzle() argument
2530 *pTileSwizzle = GetBankPipeSwizzle(bankSwizzle, pipeSwizzle, baseAddr, pTileInfo); in HwlCombineBankPipeSwizzle()
2556 ADDR_TILEINFO* pTileInfo = pIn->pTileInfo; in HwlComputeBaseSwizzle() local
2559 ADDR_ASSERT(pIn->pTileInfo); in HwlComputeBaseSwizzle()
2569 UINT_32 banks = pTileInfo ? pTileInfo->banks : 2; in HwlComputeBaseSwizzle()
2609 pipeSwizzle = pIn->surfIndex & (HwlGetPipes(pTileInfo) - 1); in HwlComputeBaseSwizzle()
2612 return HwlCombineBankPipeSwizzle(bankSwizzle, pipeSwizzle, pTileInfo, 0, &pOut->tileSwizzle); in HwlComputeBaseSwizzle()
2626 ADDR_TILEINFO* pTileInfo, ///< [in] 2D tile parameters. Client must provide all data in ExtractBankPipeSwizzle() argument
2636 UINT_32 numPipes = HwlGetPipes(pTileInfo); in ExtractBankPipeSwizzle()
2637 UINT_32 bankBits = QLog2(pTileInfo->banks); in ExtractBankPipeSwizzle()
2666 ADDR_TILEINFO* pTileInfo ///< [in] tile info in GetBankPipeSwizzle()
2669 UINT_32 pipeBits = QLog2(HwlGetPipes(pTileInfo)); in GetBankPipeSwizzle()
2693 ADDR_TILEINFO* pTileInfo ///< [in] Bank structure in ComputeSliceTileSwizzle()
2702 UINT_32 numPipes = HwlGetPipes(pTileInfo); in ComputeSliceTileSwizzle()
2703 UINT_32 numBanks = pTileInfo->banks; in ComputeSliceTileSwizzle()
2717 pTileInfo, in ComputeSliceTileSwizzle()
2738 pTileInfo); in ComputeSliceTileSwizzle()
2762 if (IsMacroTiled(pInfo->tileMode) && pInfo->pStereoInfo && pInfo->pTileInfo) in HwlComputeQbStereoRightSwizzle()
2765 pInfo->tileMode, 0, 0, pInfo->pTileInfo); in HwlComputeQbStereoRightSwizzle()
2769 HwlCombineBankPipeSwizzle(bankBits, 0, pInfo->pTileInfo, 0, &swizzle); in HwlComputeQbStereoRightSwizzle()
2796 ADDR_TILEINFO* pTileInfo ///< [in] tile info in ComputeBankFromCoord()
2799 UINT_32 pipes = HwlGetPipes(pTileInfo); in ComputeBankFromCoord()
2807 UINT_32 numBanks = pTileInfo->banks; in ComputeBankFromCoord()
2808 UINT_32 bankWidth = pTileInfo->bankWidth; in ComputeBankFromCoord()
2809 UINT_32 bankHeight = pTileInfo->bankHeight; in ComputeBankFromCoord()
2852 bank = HwlPreAdjustBank((x / MicroTileWidth), bank, pTileInfo); in ComputeBankFromCoord()
3089 surfIn.pTileInfo = pIn->pTileInfo; in DispatchComputeFmaskInfo()
3094 surfOut.pTileInfo = pOut->pTileInfo; in DispatchComputeFmaskInfo()
3158 if (pOut->pTileInfo == NULL) in HwlComputeFmaskInfo()
3160 pOut->pTileInfo = &tileInfo; in HwlComputeFmaskInfo()
3168 HwlPostCheckTileIndex(pOut->pTileInfo, pIn->tileMode, ADDR_NON_DISPLAYABLE, in HwlComputeFmaskInfo()
3173 if (pOut->pTileInfo == &tileInfo) in HwlComputeFmaskInfo()
3175 pOut->pTileInfo = NULL; in HwlComputeFmaskInfo()
3271 ADDR_TILEINFO* pTileInfo = pIn->pTileInfo; in DispatchComputeFmaskAddrFromCoord() local
3302 ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo, in DispatchComputeFmaskAddrFromCoord()
3323 pTileInfo, in DispatchComputeFmaskAddrFromCoord()
3467 ADDR_TILEINFO* pTileInfo, ///< [in] bank structure.**All fields to be valid on entry** in ComputeFmaskAddrFromCoordMacroTiled() argument
3510 pTileInfo, in ComputeFmaskAddrFromCoordMacroTiled()
3558 pTileInfo, in ComputeFmaskAddrFromCoordMacroTiled()
3674 ADDR_TILEINFO* pTileInfo, ///< [in] bank structure. **All fields to be valid on entry** in ComputeFmaskCoordFromAddrMacroTiled() argument
3714 pTileInfo, in ComputeFmaskCoordFromAddrMacroTiled()
3744 pTileInfo, in ComputeFmaskCoordFromAddrMacroTiled()
3776 ADDR_TILEINFO* pTileInfo = pIn->pTileInfo; in DispatchComputeFmaskCoordFromAddr() local
3808 ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo, in DispatchComputeFmaskCoordFromAddr()
3826 pTileInfo, in DispatchComputeFmaskCoordFromAddr()
3943 ADDR_TILEINFO* pTileInfo) in IsTileInfoAllZero() argument
3947 if (pTileInfo) in IsTileInfoAllZero()
3949 if ((pTileInfo->banks != 0) || in IsTileInfoAllZero()
3950 (pTileInfo->bankWidth != 0) || in IsTileInfoAllZero()
3951 (pTileInfo->bankHeight != 0) || in IsTileInfoAllZero()
3952 (pTileInfo->macroAspectRatio != 0) || in IsTileInfoAllZero()
3953 (pTileInfo->tileSplitBytes != 0) || in IsTileInfoAllZero()
3954 (pTileInfo->pipeConfig != 0) in IsTileInfoAllZero()
4009 ADDR_TILEINFO *pTileInfoIn = pIn->pTileInfo; in HwlConvertTileInfoToHW()
4010 ADDR_TILEINFO *pTileInfoOut = pOut->pTileInfo; in HwlConvertTileInfoToHW()
4287 if (pOut->pTileInfo == NULL) in HwlComputeSurfaceInfo()
4289 pOut->pTileInfo = &tileInfo; in HwlComputeSurfaceInfo()
4298 pOut->tileIndex = HwlPostCheckTileIndex(pOut->pTileInfo, in HwlComputeSurfaceInfo()
4309 pOut->pTileInfo); in HwlComputeSurfaceInfo()
4313 if (pOut->pTileInfo == &tileInfo) in HwlComputeSurfaceInfo()
4322 if (!IsTileInfoAllZero(pIn->pTileInfo)) in HwlComputeSurfaceInfo()
4326 ADDR_ASSERT(tileInfo.banks == pIn->pTileInfo->banks); in HwlComputeSurfaceInfo()
4327 ADDR_ASSERT(tileInfo.bankWidth == pIn->pTileInfo->bankWidth); in HwlComputeSurfaceInfo()
4328 ADDR_ASSERT(tileInfo.bankHeight == pIn->pTileInfo->bankHeight); in HwlComputeSurfaceInfo()
4329 ADDR_ASSERT(tileInfo.macroAspectRatio == pIn->pTileInfo->macroAspectRatio); in HwlComputeSurfaceInfo()
4330 ADDR_ASSERT(tileInfo.tileSplitBytes == pIn->pTileInfo->tileSplitBytes); in HwlComputeSurfaceInfo()
4334 pOut->pTileInfo = NULL; in HwlComputeSurfaceInfo()
4418 if (pIn->pTileInfo && (pIn->pTileInfo->banks > 0)) in HwlComputeSliceTileSwizzle()
4425 pIn->pTileInfo); in HwlComputeSliceTileSwizzle()
4470 ADDR_TILEINFO* pTileInfo ///< [in] Tile info in HwlComputeHtileBaseAlign()
4473 UINT_32 baseAlign = m_pipeInterleaveBytes * HwlGetPipes(pTileInfo); in HwlComputeHtileBaseAlign()
4477 ADDR_ASSERT(pTileInfo != NULL); in HwlComputeHtileBaseAlign()
4478 if (pTileInfo) in HwlComputeHtileBaseAlign()
4480 baseAlign *= pTileInfo->banks; in HwlComputeHtileBaseAlign()