Lines Matching refs:val
851 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC() argument
853 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; in A4XX_CGC_HLSQ_EARLY_CYC()
908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
910 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WID… in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
914 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
916 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HE… in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
930 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH() argument
932 assert(!(val & 0x1f)); in A4XX_RB_MODE_CONTROL_WIDTH()
933 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; in A4XX_RB_MODE_CONTROL_WIDTH()
937 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT() argument
939 assert(!(val & 0x1f)); in A4XX_RB_MODE_CONTROL_HEIGHT()
940 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; in A4XX_RB_MODE_CONTROL_HEIGHT()
952 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) in A4XX_RB_MSAA_CONTROL_SAMPLES() argument
954 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; in A4XX_RB_MSAA_CONTROL_SAMPLES()
967 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) in A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES() argument
969 …return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPL… in A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES()
983 static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) in A4XX_RB_MRT_CONTROL_ROP_CODE() argument
985 return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK; in A4XX_RB_MRT_CONTROL_ROP_CODE()
989 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) in A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE() argument
991 …return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENAB… in A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE()
997 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) in A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT() argument
999 …return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MA… in A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT()
1003 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) in A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE() argument
1005 …return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MO… in A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE()
1009 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) in A4XX_RB_MRT_BUF_INFO_DITHER_MODE() argument
1011 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; in A4XX_RB_MRT_BUF_INFO_DITHER_MODE()
1015 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) in A4XX_RB_MRT_BUF_INFO_COLOR_SWAP() argument
1017 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; in A4XX_RB_MRT_BUF_INFO_COLOR_SWAP()
1022 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) in A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH() argument
1024 assert(!(val & 0xf)); in A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH()
1025 …return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BU… in A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH()
1033 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) in A4XX_RB_MRT_CONTROL3_STRIDE() argument
1035 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; in A4XX_RB_MRT_CONTROL3_STRIDE()
1041 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) in A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR() argument
1043 …return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_… in A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR()
1047 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) in A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE() argument
1049 …return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RG… in A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE()
1053 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) in A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR() argument
1055 …return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB… in A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR()
1059 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) in A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR() argument
1061 …return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_AL… in A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR()
1065 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) in A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE() argument
1067 …return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_… in A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE()
1071 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) in A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR() argument
1073 …return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_A… in A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR()
1079 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) in A4XX_RB_BLEND_RED_UINT() argument
1081 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; in A4XX_RB_BLEND_RED_UINT()
1085 static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) in A4XX_RB_BLEND_RED_SINT() argument
1087 return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK; in A4XX_RB_BLEND_RED_SINT()
1091 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) in A4XX_RB_BLEND_RED_FLOAT() argument
1093 …return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MA… in A4XX_RB_BLEND_RED_FLOAT()
1099 static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) in A4XX_RB_BLEND_RED_F32() argument
1101 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK; in A4XX_RB_BLEND_RED_F32()
1107 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) in A4XX_RB_BLEND_GREEN_UINT() argument
1109 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; in A4XX_RB_BLEND_GREEN_UINT()
1113 static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) in A4XX_RB_BLEND_GREEN_SINT() argument
1115 return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK; in A4XX_RB_BLEND_GREEN_SINT()
1119 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) in A4XX_RB_BLEND_GREEN_FLOAT() argument
1121 …return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT… in A4XX_RB_BLEND_GREEN_FLOAT()
1127 static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) in A4XX_RB_BLEND_GREEN_F32() argument
1129 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK; in A4XX_RB_BLEND_GREEN_F32()
1135 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) in A4XX_RB_BLEND_BLUE_UINT() argument
1137 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; in A4XX_RB_BLEND_BLUE_UINT()
1141 static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) in A4XX_RB_BLEND_BLUE_SINT() argument
1143 return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK; in A4XX_RB_BLEND_BLUE_SINT()
1147 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) in A4XX_RB_BLEND_BLUE_FLOAT() argument
1149 …return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__… in A4XX_RB_BLEND_BLUE_FLOAT()
1155 static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) in A4XX_RB_BLEND_BLUE_F32() argument
1157 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK; in A4XX_RB_BLEND_BLUE_F32()
1163 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) in A4XX_RB_BLEND_ALPHA_UINT() argument
1165 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; in A4XX_RB_BLEND_ALPHA_UINT()
1169 static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) in A4XX_RB_BLEND_ALPHA_SINT() argument
1171 return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK; in A4XX_RB_BLEND_ALPHA_SINT()
1175 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) in A4XX_RB_BLEND_ALPHA_FLOAT() argument
1177 …return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT… in A4XX_RB_BLEND_ALPHA_FLOAT()
1183 static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val) in A4XX_RB_BLEND_ALPHA_F32() argument
1185 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK; in A4XX_RB_BLEND_ALPHA_F32()
1191 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) in A4XX_RB_ALPHA_CONTROL_ALPHA_REF() argument
1193 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; in A4XX_RB_ALPHA_CONTROL_ALPHA_REF()
1198 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) in A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC() argument
1200 …return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_… in A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC()
1206 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) in A4XX_RB_FS_OUTPUT_ENABLE_BLEND() argument
1208 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; in A4XX_RB_FS_OUTPUT_ENABLE_BLEND()
1213 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) in A4XX_RB_FS_OUTPUT_SAMPLE_MASK() argument
1215 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; in A4XX_RB_FS_OUTPUT_SAMPLE_MASK()
1222 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) in A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR() argument
1224 assert(!(val & 0x3)); in A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR()
1225 …return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADD… in A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR()
1231 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) in A4XX_RB_RENDER_COMPONENTS_RT0() argument
1233 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; in A4XX_RB_RENDER_COMPONENTS_RT0()
1237 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) in A4XX_RB_RENDER_COMPONENTS_RT1() argument
1239 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; in A4XX_RB_RENDER_COMPONENTS_RT1()
1243 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) in A4XX_RB_RENDER_COMPONENTS_RT2() argument
1245 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; in A4XX_RB_RENDER_COMPONENTS_RT2()
1249 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) in A4XX_RB_RENDER_COMPONENTS_RT3() argument
1251 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; in A4XX_RB_RENDER_COMPONENTS_RT3()
1255 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) in A4XX_RB_RENDER_COMPONENTS_RT4() argument
1257 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; in A4XX_RB_RENDER_COMPONENTS_RT4()
1261 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) in A4XX_RB_RENDER_COMPONENTS_RT5() argument
1263 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; in A4XX_RB_RENDER_COMPONENTS_RT5()
1267 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) in A4XX_RB_RENDER_COMPONENTS_RT6() argument
1269 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; in A4XX_RB_RENDER_COMPONENTS_RT6()
1273 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) in A4XX_RB_RENDER_COMPONENTS_RT7() argument
1275 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; in A4XX_RB_RENDER_COMPONENTS_RT7()
1281 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) in A4XX_RB_COPY_CONTROL_MSAA_RESOLVE() argument
1283 …return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MA… in A4XX_RB_COPY_CONTROL_MSAA_RESOLVE()
1287 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) in A4XX_RB_COPY_CONTROL_MODE() argument
1289 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; in A4XX_RB_COPY_CONTROL_MODE()
1293 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) in A4XX_RB_COPY_CONTROL_FASTCLEAR() argument
1295 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; in A4XX_RB_COPY_CONTROL_FASTCLEAR()
1299 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) in A4XX_RB_COPY_CONTROL_GMEM_BASE() argument
1301 assert(!(val & 0x3fff)); in A4XX_RB_COPY_CONTROL_GMEM_BASE()
1302 …return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MA… in A4XX_RB_COPY_CONTROL_GMEM_BASE()
1308 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) in A4XX_RB_COPY_DEST_BASE_BASE() argument
1310 assert(!(val & 0x1f)); in A4XX_RB_COPY_DEST_BASE_BASE()
1311 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; in A4XX_RB_COPY_DEST_BASE_BASE()
1317 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) in A4XX_RB_COPY_DEST_PITCH_PITCH() argument
1319 assert(!(val & 0x1f)); in A4XX_RB_COPY_DEST_PITCH_PITCH()
1320 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; in A4XX_RB_COPY_DEST_PITCH_PITCH()
1326 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) in A4XX_RB_COPY_DEST_INFO_FORMAT() argument
1328 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; in A4XX_RB_COPY_DEST_INFO_FORMAT()
1332 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) in A4XX_RB_COPY_DEST_INFO_SWAP() argument
1334 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; in A4XX_RB_COPY_DEST_INFO_SWAP()
1338 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) in A4XX_RB_COPY_DEST_INFO_DITHER_MODE() argument
1340 …return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__… in A4XX_RB_COPY_DEST_INFO_DITHER_MODE()
1344 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) in A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE() argument
1346 …return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONEN… in A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE()
1350 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) in A4XX_RB_COPY_DEST_INFO_ENDIAN() argument
1352 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; in A4XX_RB_COPY_DEST_INFO_ENDIAN()
1356 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) in A4XX_RB_COPY_DEST_INFO_TILE() argument
1358 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; in A4XX_RB_COPY_DEST_INFO_TILE()
1364 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) in A4XX_RB_FS_OUTPUT_REG_MRT() argument
1366 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; in A4XX_RB_FS_OUTPUT_REG_MRT()
1376 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) in A4XX_RB_DEPTH_CONTROL_ZFUNC() argument
1378 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; in A4XX_RB_DEPTH_CONTROL_ZFUNC()
1390 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) in A4XX_RB_DEPTH_INFO_DEPTH_FORMAT() argument
1392 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; in A4XX_RB_DEPTH_INFO_DEPTH_FORMAT()
1396 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) in A4XX_RB_DEPTH_INFO_DEPTH_BASE() argument
1398 assert(!(val & 0xfff)); in A4XX_RB_DEPTH_INFO_DEPTH_BASE()
1399 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; in A4XX_RB_DEPTH_INFO_DEPTH_BASE()
1405 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) in A4XX_RB_DEPTH_PITCH() argument
1407 assert(!(val & 0x1f)); in A4XX_RB_DEPTH_PITCH()
1408 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; in A4XX_RB_DEPTH_PITCH()
1414 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) in A4XX_RB_DEPTH_PITCH2() argument
1416 assert(!(val & 0x1f)); in A4XX_RB_DEPTH_PITCH2()
1417 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; in A4XX_RB_DEPTH_PITCH2()
1426 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) in A4XX_RB_STENCIL_CONTROL_FUNC() argument
1428 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; in A4XX_RB_STENCIL_CONTROL_FUNC()
1432 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) in A4XX_RB_STENCIL_CONTROL_FAIL() argument
1434 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; in A4XX_RB_STENCIL_CONTROL_FAIL()
1438 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) in A4XX_RB_STENCIL_CONTROL_ZPASS() argument
1440 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; in A4XX_RB_STENCIL_CONTROL_ZPASS()
1444 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) in A4XX_RB_STENCIL_CONTROL_ZFAIL() argument
1446 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; in A4XX_RB_STENCIL_CONTROL_ZFAIL()
1450 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) in A4XX_RB_STENCIL_CONTROL_FUNC_BF() argument
1452 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; in A4XX_RB_STENCIL_CONTROL_FUNC_BF()
1456 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) in A4XX_RB_STENCIL_CONTROL_FAIL_BF() argument
1458 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; in A4XX_RB_STENCIL_CONTROL_FAIL_BF()
1462 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) in A4XX_RB_STENCIL_CONTROL_ZPASS_BF() argument
1464 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; in A4XX_RB_STENCIL_CONTROL_ZPASS_BF()
1468 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) in A4XX_RB_STENCIL_CONTROL_ZFAIL_BF() argument
1470 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; in A4XX_RB_STENCIL_CONTROL_ZFAIL_BF()
1480 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) in A4XX_RB_STENCIL_INFO_STENCIL_BASE() argument
1482 assert(!(val & 0xfff)); in A4XX_RB_STENCIL_INFO_STENCIL_BASE()
1483 …return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BA… in A4XX_RB_STENCIL_INFO_STENCIL_BASE()
1489 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) in A4XX_RB_STENCIL_PITCH() argument
1491 assert(!(val & 0x1f)); in A4XX_RB_STENCIL_PITCH()
1492 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; in A4XX_RB_STENCIL_PITCH()
1498 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) in A4XX_RB_STENCILREFMASK_STENCILREF() argument
1500 …return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MA… in A4XX_RB_STENCILREFMASK_STENCILREF()
1504 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) in A4XX_RB_STENCILREFMASK_STENCILMASK() argument
1506 …return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__… in A4XX_RB_STENCILREFMASK_STENCILMASK()
1510 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) in A4XX_RB_STENCILREFMASK_STENCILWRITEMASK() argument
1512 …return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILW… in A4XX_RB_STENCILREFMASK_STENCILWRITEMASK()
1518 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) in A4XX_RB_STENCILREFMASK_BF_STENCILREF() argument
1520 …return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILR… in A4XX_RB_STENCILREFMASK_BF_STENCILREF()
1524 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) in A4XX_RB_STENCILREFMASK_BF_STENCILMASK() argument
1526 …return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCIL… in A4XX_RB_STENCILREFMASK_BF_STENCILMASK()
1530 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) in A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK() argument
1532 …return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_ST… in A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK()
1539 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) in A4XX_RB_BIN_OFFSET_X() argument
1541 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; in A4XX_RB_BIN_OFFSET_X()
1545 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) in A4XX_RB_BIN_OFFSET_Y() argument
1547 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; in A4XX_RB_BIN_OFFSET_Y()
2219 static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A4XX_CP_PROTECT_REG_BASE_ADDR() argument
2221 return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK; in A4XX_CP_PROTECT_REG_BASE_ADDR()
2225 static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A4XX_CP_PROTECT_REG_MASK_LEN() argument
2227 return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK; in A4XX_CP_PROTECT_REG_MASK_LEN()
2309 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) in A4XX_SP_VS_CTRL_REG0_THREADMODE() argument
2311 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; in A4XX_SP_VS_CTRL_REG0_THREADMODE()
2317 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) in A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT() argument
2319 …return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTP… in A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT()
2323 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) in A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT() argument
2325 …return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTP… in A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT()
2329 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) in A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP() argument
2331 …return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERL… in A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP()
2335 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) in A4XX_SP_VS_CTRL_REG0_THREADSIZE() argument
2337 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; in A4XX_SP_VS_CTRL_REG0_THREADSIZE()
2345 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) in A4XX_SP_VS_CTRL_REG1_CONSTLENGTH() argument
2347 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; in A4XX_SP_VS_CTRL_REG1_CONSTLENGTH()
2351 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) in A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING() argument
2353 …return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUT… in A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING()
2359 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) in A4XX_SP_VS_PARAM_REG_POSREGID() argument
2361 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; in A4XX_SP_VS_PARAM_REG_POSREGID()
2365 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) in A4XX_SP_VS_PARAM_REG_PSIZEREGID() argument
2367 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; in A4XX_SP_VS_PARAM_REG_PSIZEREGID()
2371 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) in A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR() argument
2373 …return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__… in A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR()
2381 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) in A4XX_SP_VS_OUT_REG_A_REGID() argument
2383 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; in A4XX_SP_VS_OUT_REG_A_REGID()
2387 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) in A4XX_SP_VS_OUT_REG_A_COMPMASK() argument
2389 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; in A4XX_SP_VS_OUT_REG_A_COMPMASK()
2393 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) in A4XX_SP_VS_OUT_REG_B_REGID() argument
2395 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; in A4XX_SP_VS_OUT_REG_B_REGID()
2399 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) in A4XX_SP_VS_OUT_REG_B_COMPMASK() argument
2401 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; in A4XX_SP_VS_OUT_REG_B_COMPMASK()
2409 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) in A4XX_SP_VS_VPC_DST_REG_OUTLOC0() argument
2411 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; in A4XX_SP_VS_VPC_DST_REG_OUTLOC0()
2415 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) in A4XX_SP_VS_VPC_DST_REG_OUTLOC1() argument
2417 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; in A4XX_SP_VS_VPC_DST_REG_OUTLOC1()
2421 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) in A4XX_SP_VS_VPC_DST_REG_OUTLOC2() argument
2423 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; in A4XX_SP_VS_VPC_DST_REG_OUTLOC2()
2427 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) in A4XX_SP_VS_VPC_DST_REG_OUTLOC3() argument
2429 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; in A4XX_SP_VS_VPC_DST_REG_OUTLOC3()
2435 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) in A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
2437 …return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_C… in A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
2441 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) in A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
2443 …return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHA… in A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
2457 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) in A4XX_SP_FS_CTRL_REG0_THREADMODE() argument
2459 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; in A4XX_SP_FS_CTRL_REG0_THREADMODE()
2465 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) in A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT() argument
2467 …return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTP… in A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT()
2471 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) in A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT() argument
2473 …return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTP… in A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT()
2477 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) in A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP() argument
2479 …return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERL… in A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP()
2483 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) in A4XX_SP_FS_CTRL_REG0_THREADSIZE() argument
2485 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; in A4XX_SP_FS_CTRL_REG0_THREADSIZE()
2493 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) in A4XX_SP_FS_CTRL_REG1_CONSTLENGTH() argument
2495 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; in A4XX_SP_FS_CTRL_REG1_CONSTLENGTH()
2504 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) in A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
2506 …return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_C… in A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
2510 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) in A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
2512 …return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHA… in A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
2526 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) in A4XX_SP_FS_OUTPUT_REG_MRT() argument
2528 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; in A4XX_SP_FS_OUTPUT_REG_MRT()
2533 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) in A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID() argument
2535 …return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MA… in A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID()
2539 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) in A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID() argument
2541 …return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK… in A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID()
2549 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) in A4XX_SP_FS_MRT_REG_REGID() argument
2551 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; in A4XX_SP_FS_MRT_REG_REGID()
2556 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) in A4XX_SP_FS_MRT_REG_MRTFORMAT() argument
2558 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; in A4XX_SP_FS_MRT_REG_MRTFORMAT()
2579 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) in A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
2581 …return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_C… in A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
2585 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) in A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
2587 …return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHA… in A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
2601 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) in A4XX_SP_DS_PARAM_REG_POSREGID() argument
2603 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK; in A4XX_SP_DS_PARAM_REG_POSREGID()
2607 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) in A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR() argument
2609 …return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__… in A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR()
2617 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) in A4XX_SP_DS_OUT_REG_A_REGID() argument
2619 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK; in A4XX_SP_DS_OUT_REG_A_REGID()
2623 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) in A4XX_SP_DS_OUT_REG_A_COMPMASK() argument
2625 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK; in A4XX_SP_DS_OUT_REG_A_COMPMASK()
2629 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) in A4XX_SP_DS_OUT_REG_B_REGID() argument
2631 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK; in A4XX_SP_DS_OUT_REG_B_REGID()
2635 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) in A4XX_SP_DS_OUT_REG_B_COMPMASK() argument
2637 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; in A4XX_SP_DS_OUT_REG_B_COMPMASK()
2645 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) in A4XX_SP_DS_VPC_DST_REG_OUTLOC0() argument
2647 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; in A4XX_SP_DS_VPC_DST_REG_OUTLOC0()
2651 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) in A4XX_SP_DS_VPC_DST_REG_OUTLOC1() argument
2653 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; in A4XX_SP_DS_VPC_DST_REG_OUTLOC1()
2657 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) in A4XX_SP_DS_VPC_DST_REG_OUTLOC2() argument
2659 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; in A4XX_SP_DS_VPC_DST_REG_OUTLOC2()
2663 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) in A4XX_SP_DS_VPC_DST_REG_OUTLOC3() argument
2665 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; in A4XX_SP_DS_VPC_DST_REG_OUTLOC3()
2671 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) in A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
2673 …return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_C… in A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
2677 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) in A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
2679 …return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHA… in A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
2693 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) in A4XX_SP_GS_PARAM_REG_POSREGID() argument
2695 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK; in A4XX_SP_GS_PARAM_REG_POSREGID()
2699 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) in A4XX_SP_GS_PARAM_REG_PRIMREGID() argument
2701 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK; in A4XX_SP_GS_PARAM_REG_PRIMREGID()
2705 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) in A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR() argument
2707 …return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__… in A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR()
2715 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) in A4XX_SP_GS_OUT_REG_A_REGID() argument
2717 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK; in A4XX_SP_GS_OUT_REG_A_REGID()
2721 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) in A4XX_SP_GS_OUT_REG_A_COMPMASK() argument
2723 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK; in A4XX_SP_GS_OUT_REG_A_COMPMASK()
2727 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) in A4XX_SP_GS_OUT_REG_B_REGID() argument
2729 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK; in A4XX_SP_GS_OUT_REG_B_REGID()
2733 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) in A4XX_SP_GS_OUT_REG_B_COMPMASK() argument
2735 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; in A4XX_SP_GS_OUT_REG_B_COMPMASK()
2743 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) in A4XX_SP_GS_VPC_DST_REG_OUTLOC0() argument
2745 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; in A4XX_SP_GS_VPC_DST_REG_OUTLOC0()
2749 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) in A4XX_SP_GS_VPC_DST_REG_OUTLOC1() argument
2751 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; in A4XX_SP_GS_VPC_DST_REG_OUTLOC1()
2755 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) in A4XX_SP_GS_VPC_DST_REG_OUTLOC2() argument
2757 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; in A4XX_SP_GS_VPC_DST_REG_OUTLOC2()
2761 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) in A4XX_SP_GS_VPC_DST_REG_OUTLOC3() argument
2763 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; in A4XX_SP_GS_VPC_DST_REG_OUTLOC3()
2769 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) in A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
2771 …return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_C… in A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
2775 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) in A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
2777 …return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHA… in A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
2805 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) in A4XX_VPC_ATTR_TOTALATTR() argument
2807 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; in A4XX_VPC_ATTR_TOTALATTR()
2812 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) in A4XX_VPC_ATTR_THRDASSIGN() argument
2814 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; in A4XX_VPC_ATTR_THRDASSIGN()
2821 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) in A4XX_VPC_PACK_NUMBYPASSVAR() argument
2823 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; in A4XX_VPC_PACK_NUMBYPASSVAR()
2827 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) in A4XX_VPC_PACK_NUMFPNONPOSVAR() argument
2829 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; in A4XX_VPC_PACK_NUMFPNONPOSVAR()
2833 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) in A4XX_VPC_PACK_NUMNONPOSVSVAR() argument
2835 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; in A4XX_VPC_PACK_NUMNONPOSVSVAR()
2851 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) in A4XX_VSC_BIN_SIZE_WIDTH() argument
2853 assert(!(val & 0x1f)); in A4XX_VSC_BIN_SIZE_WIDTH()
2854 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; in A4XX_VSC_BIN_SIZE_WIDTH()
2858 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) in A4XX_VSC_BIN_SIZE_HEIGHT() argument
2860 assert(!(val & 0x1f)); in A4XX_VSC_BIN_SIZE_HEIGHT()
2861 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; in A4XX_VSC_BIN_SIZE_HEIGHT()
2875 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) in A4XX_VSC_PIPE_CONFIG_REG_X() argument
2877 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; in A4XX_VSC_PIPE_CONFIG_REG_X()
2881 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) in A4XX_VSC_PIPE_CONFIG_REG_Y() argument
2883 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; in A4XX_VSC_PIPE_CONFIG_REG_Y()
2887 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) in A4XX_VSC_PIPE_CONFIG_REG_W() argument
2889 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; in A4XX_VSC_PIPE_CONFIG_REG_W()
2893 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) in A4XX_VSC_PIPE_CONFIG_REG_H() argument
2895 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; in A4XX_VSC_PIPE_CONFIG_REG_H()
2937 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) in A4XX_VFD_CONTROL_0_TOTALATTRTOVS() argument
2939 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; in A4XX_VFD_CONTROL_0_TOTALATTRTOVS()
2943 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) in A4XX_VFD_CONTROL_0_BYPASSATTROVS() argument
2945 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; in A4XX_VFD_CONTROL_0_BYPASSATTROVS()
2949 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) in A4XX_VFD_CONTROL_0_STRMDECINSTRCNT() argument
2951 …return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__… in A4XX_VFD_CONTROL_0_STRMDECINSTRCNT()
2955 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) in A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT() argument
2957 …return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRC… in A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT()
2963 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) in A4XX_VFD_CONTROL_1_MAXSTORAGE() argument
2965 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; in A4XX_VFD_CONTROL_1_MAXSTORAGE()
2969 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) in A4XX_VFD_CONTROL_1_REGID4VTX() argument
2971 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; in A4XX_VFD_CONTROL_1_REGID4VTX()
2975 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) in A4XX_VFD_CONTROL_1_REGID4INST() argument
2977 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; in A4XX_VFD_CONTROL_1_REGID4INST()
2985 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) in A4XX_VFD_CONTROL_3_REGID_VTXCNT() argument
2987 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; in A4XX_VFD_CONTROL_3_REGID_VTXCNT()
2991 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) in A4XX_VFD_CONTROL_3_REGID_TESSX() argument
2993 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK; in A4XX_VFD_CONTROL_3_REGID_TESSX()
2997 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) in A4XX_VFD_CONTROL_3_REGID_TESSY() argument
2999 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK; in A4XX_VFD_CONTROL_3_REGID_TESSY()
3011 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) in A4XX_VFD_FETCH_INSTR_0_FETCHSIZE() argument
3013 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; in A4XX_VFD_FETCH_INSTR_0_FETCHSIZE()
3017 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) in A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE() argument
3019 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; in A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE()
3029 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) in A4XX_VFD_FETCH_INSTR_2_SIZE() argument
3031 return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; in A4XX_VFD_FETCH_INSTR_2_SIZE()
3037 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) in A4XX_VFD_FETCH_INSTR_3_STEPRATE() argument
3039 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; in A4XX_VFD_FETCH_INSTR_3_STEPRATE()
3047 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) in A4XX_VFD_DECODE_INSTR_WRITEMASK() argument
3049 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; in A4XX_VFD_DECODE_INSTR_WRITEMASK()
3054 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) in A4XX_VFD_DECODE_INSTR_FORMAT() argument
3056 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; in A4XX_VFD_DECODE_INSTR_FORMAT()
3060 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) in A4XX_VFD_DECODE_INSTR_REGID() argument
3062 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; in A4XX_VFD_DECODE_INSTR_REGID()
3067 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) in A4XX_VFD_DECODE_INSTR_SWAP() argument
3069 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; in A4XX_VFD_DECODE_INSTR_SWAP()
3073 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) in A4XX_VFD_DECODE_INSTR_SHIFTCNT() argument
3075 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; in A4XX_VFD_DECODE_INSTR_SHIFTCNT()
3105 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) in A4XX_TPL1_TP_TEX_COUNT_VS() argument
3107 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; in A4XX_TPL1_TP_TEX_COUNT_VS()
3111 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) in A4XX_TPL1_TP_TEX_COUNT_HS() argument
3113 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; in A4XX_TPL1_TP_TEX_COUNT_HS()
3117 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) in A4XX_TPL1_TP_TEX_COUNT_DS() argument
3119 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; in A4XX_TPL1_TP_TEX_COUNT_DS()
3123 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) in A4XX_TPL1_TP_TEX_COUNT_GS() argument
3125 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; in A4XX_TPL1_TP_TEX_COUNT_GS()
3178 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
3180 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
3184 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A4XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
3186 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A4XX_GRAS_CL_GB_CLIP_ADJ_VERT()
3192 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) in A4XX_GRAS_CL_VPORT_XOFFSET_0() argument
3194 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; in A4XX_GRAS_CL_VPORT_XOFFSET_0()
3200 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) in A4XX_GRAS_CL_VPORT_XSCALE_0() argument
3202 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; in A4XX_GRAS_CL_VPORT_XSCALE_0()
3208 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) in A4XX_GRAS_CL_VPORT_YOFFSET_0() argument
3210 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; in A4XX_GRAS_CL_VPORT_YOFFSET_0()
3216 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) in A4XX_GRAS_CL_VPORT_YSCALE_0() argument
3218 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; in A4XX_GRAS_CL_VPORT_YSCALE_0()
3224 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) in A4XX_GRAS_CL_VPORT_ZOFFSET_0() argument
3226 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; in A4XX_GRAS_CL_VPORT_ZOFFSET_0()
3232 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) in A4XX_GRAS_CL_VPORT_ZSCALE_0() argument
3234 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; in A4XX_GRAS_CL_VPORT_ZSCALE_0()
3240 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) in A4XX_GRAS_SU_POINT_MINMAX_MIN() argument
3242 …return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_M… in A4XX_GRAS_SU_POINT_MINMAX_MIN()
3246 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) in A4XX_GRAS_SU_POINT_MINMAX_MAX() argument
3248 …return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_M… in A4XX_GRAS_SU_POINT_MINMAX_MAX()
3254 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) in A4XX_GRAS_SU_POINT_SIZE() argument
3256 …return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MA… in A4XX_GRAS_SU_POINT_SIZE()
3266 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) in A4XX_GRAS_SU_POLY_OFFSET_SCALE() argument
3268 …return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MAS… in A4XX_GRAS_SU_POLY_OFFSET_SCALE()
3274 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) in A4XX_GRAS_SU_POLY_OFFSET_OFFSET() argument
3276 …return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__M… in A4XX_GRAS_SU_POLY_OFFSET_OFFSET()
3282 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) in A4XX_GRAS_SU_POLY_OFFSET_CLAMP() argument
3284 …return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MAS… in A4XX_GRAS_SU_POLY_OFFSET_CLAMP()
3290 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) in A4XX_GRAS_DEPTH_CONTROL_FORMAT() argument
3292 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; in A4XX_GRAS_DEPTH_CONTROL_FORMAT()
3301 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) in A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH() argument
3303 …return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU… in A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH()
3312 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) in A4XX_GRAS_SC_CONTROL_RENDER_MODE() argument
3314 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; in A4XX_GRAS_SC_CONTROL_RENDER_MODE()
3318 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) in A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES() argument
3320 …return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MA… in A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES()
3325 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) in A4XX_GRAS_SC_CONTROL_RASTER_MODE() argument
3327 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; in A4XX_GRAS_SC_CONTROL_RASTER_MODE()
3334 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) in A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X() argument
3336 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; in A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X()
3340 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) in A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y() argument
3342 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; in A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y()
3349 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) in A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X() argument
3351 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; in A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X()
3355 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) in A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y() argument
3357 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; in A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y()
3364 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) in A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X() argument
3366 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; in A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X()
3370 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) in A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y() argument
3372 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; in A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y()
3379 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) in A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X() argument
3381 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; in A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X()
3385 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) in A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y() argument
3387 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; in A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y()
3394 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) in A4XX_GRAS_SC_EXTENT_WINDOW_BR_X() argument
3396 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; in A4XX_GRAS_SC_EXTENT_WINDOW_BR_X()
3400 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) in A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y() argument
3402 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; in A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y()
3409 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) in A4XX_GRAS_SC_EXTENT_WINDOW_TL_X() argument
3411 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; in A4XX_GRAS_SC_EXTENT_WINDOW_TL_X()
3415 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) in A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y() argument
3417 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; in A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y()
3477 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) in A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE() argument
3479 …return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSI… in A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE()
3487 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) in A4XX_HLSQ_CONTROL_0_REG_CONSTMODE() argument
3489 …return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MA… in A4XX_HLSQ_CONTROL_0_REG_CONSTMODE()
3499 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) in A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE() argument
3501 …return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSI… in A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE()
3507 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) in A4XX_HLSQ_CONTROL_1_REG_COORDREGID() argument
3509 …return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__… in A4XX_HLSQ_CONTROL_1_REG_COORDREGID()
3513 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) in A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID() argument
3515 …return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREG… in A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID()
3521 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) in A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD() argument
3523 …return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIM… in A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD()
3527 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) in A4XX_HLSQ_CONTROL_2_REG_FACEREGID() argument
3529 …return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MA… in A4XX_HLSQ_CONTROL_2_REG_FACEREGID()
3533 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) in A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID() argument
3535 …return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID… in A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID()
3539 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) in A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID() argument
3541 …return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLE… in A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID()
3547 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) in A4XX_HLSQ_CONTROL_3_REG_REGID() argument
3549 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; in A4XX_HLSQ_CONTROL_3_REG_REGID()
3557 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) in A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH() argument
3559 …return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENG… in A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH()
3563 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) in A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET() argument
3565 …return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CON… in A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET()
3570 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) in A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET() argument
3572 …return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADE… in A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET()
3576 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) in A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH() argument
3578 …return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENG… in A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH()
3584 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) in A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH() argument
3586 …return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENG… in A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH()
3590 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) in A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET() argument
3592 …return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CON… in A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET()
3597 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) in A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET() argument
3599 …return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADE… in A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET()
3603 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) in A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH() argument
3605 …return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENG… in A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH()
3611 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) in A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH() argument
3613 …return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENG… in A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH()
3617 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) in A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET() argument
3619 …return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CON… in A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET()
3624 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) in A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET() argument
3626 …return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADE… in A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET()
3630 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) in A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH() argument
3632 …return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENG… in A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH()
3638 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) in A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH() argument
3640 …return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENG… in A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH()
3644 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) in A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET() argument
3646 …return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CON… in A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET()
3651 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) in A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET() argument
3653 …return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADE… in A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET()
3657 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) in A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH() argument
3659 …return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENG… in A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH()
3665 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) in A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH() argument
3667 …return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENG… in A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH()
3671 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) in A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET() argument
3673 …return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CON… in A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET()
3678 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) in A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET() argument
3680 …return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADE… in A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET()
3684 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) in A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH() argument
3686 …return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENG… in A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH()
3749 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) in A4XX_PC_VSTREAM_CONTROL_SIZE() argument
3751 return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK; in A4XX_PC_VSTREAM_CONTROL_SIZE()
3755 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) in A4XX_PC_VSTREAM_CONTROL_N() argument
3757 return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK; in A4XX_PC_VSTREAM_CONTROL_N()
3763 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) in A4XX_PC_PRIM_VTX_CNTL_VAROUT() argument
3765 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; in A4XX_PC_PRIM_VTX_CNTL_VAROUT()
3774 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) in A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE() argument
3776 …return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLY… in A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE()
3780 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) in A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE() argument
3782 …return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYM… in A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE()
3791 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) in A4XX_PC_GS_PARAM_MAX_VERTICES() argument
3793 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; in A4XX_PC_GS_PARAM_MAX_VERTICES()
3797 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) in A4XX_PC_GS_PARAM_INVOCATIONS() argument
3799 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; in A4XX_PC_GS_PARAM_INVOCATIONS()
3803 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) in A4XX_PC_GS_PARAM_PRIMTYPE() argument
3805 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; in A4XX_PC_GS_PARAM_PRIMTYPE()
3812 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) in A4XX_PC_HS_PARAM_VERTICES_OUT() argument
3814 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; in A4XX_PC_HS_PARAM_VERTICES_OUT()
3818 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) in A4XX_PC_HS_PARAM_SPACING() argument
3820 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; in A4XX_PC_HS_PARAM_SPACING()
3888 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) in A4XX_TEX_SAMP_0_XY_MAG() argument
3890 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; in A4XX_TEX_SAMP_0_XY_MAG()
3894 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) in A4XX_TEX_SAMP_0_XY_MIN() argument
3896 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; in A4XX_TEX_SAMP_0_XY_MIN()
3900 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) in A4XX_TEX_SAMP_0_WRAP_S() argument
3902 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; in A4XX_TEX_SAMP_0_WRAP_S()
3906 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) in A4XX_TEX_SAMP_0_WRAP_T() argument
3908 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; in A4XX_TEX_SAMP_0_WRAP_T()
3912 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) in A4XX_TEX_SAMP_0_WRAP_R() argument
3914 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; in A4XX_TEX_SAMP_0_WRAP_R()
3918 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) in A4XX_TEX_SAMP_0_ANISO() argument
3920 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; in A4XX_TEX_SAMP_0_ANISO()
3924 static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val) in A4XX_TEX_SAMP_0_LOD_BIAS() argument
3926 …return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS_… in A4XX_TEX_SAMP_0_LOD_BIAS()
3932 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) in A4XX_TEX_SAMP_1_COMPARE_FUNC() argument
3934 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; in A4XX_TEX_SAMP_1_COMPARE_FUNC()
3941 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) in A4XX_TEX_SAMP_1_MAX_LOD() argument
3943 …return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__… in A4XX_TEX_SAMP_1_MAX_LOD()
3947 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) in A4XX_TEX_SAMP_1_MIN_LOD() argument
3949 …return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__… in A4XX_TEX_SAMP_1_MIN_LOD()
3957 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) in A4XX_TEX_CONST_0_SWIZ_X() argument
3959 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; in A4XX_TEX_CONST_0_SWIZ_X()
3963 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) in A4XX_TEX_CONST_0_SWIZ_Y() argument
3965 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; in A4XX_TEX_CONST_0_SWIZ_Y()
3969 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) in A4XX_TEX_CONST_0_SWIZ_Z() argument
3971 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; in A4XX_TEX_CONST_0_SWIZ_Z()
3975 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) in A4XX_TEX_CONST_0_SWIZ_W() argument
3977 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; in A4XX_TEX_CONST_0_SWIZ_W()
3981 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) in A4XX_TEX_CONST_0_MIPLVLS() argument
3983 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; in A4XX_TEX_CONST_0_MIPLVLS()
3987 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) in A4XX_TEX_CONST_0_FMT() argument
3989 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; in A4XX_TEX_CONST_0_FMT()
3993 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) in A4XX_TEX_CONST_0_TYPE() argument
3995 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; in A4XX_TEX_CONST_0_TYPE()
4001 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) in A4XX_TEX_CONST_1_HEIGHT() argument
4003 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; in A4XX_TEX_CONST_1_HEIGHT()
4007 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) in A4XX_TEX_CONST_1_WIDTH() argument
4009 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; in A4XX_TEX_CONST_1_WIDTH()
4015 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) in A4XX_TEX_CONST_2_FETCHSIZE() argument
4017 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; in A4XX_TEX_CONST_2_FETCHSIZE()
4021 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) in A4XX_TEX_CONST_2_PITCH() argument
4023 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; in A4XX_TEX_CONST_2_PITCH()
4027 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) in A4XX_TEX_CONST_2_SWAP() argument
4029 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; in A4XX_TEX_CONST_2_SWAP()
4035 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) in A4XX_TEX_CONST_3_LAYERSZ() argument
4037 assert(!(val & 0xfff)); in A4XX_TEX_CONST_3_LAYERSZ()
4038 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; in A4XX_TEX_CONST_3_LAYERSZ()
4042 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) in A4XX_TEX_CONST_3_DEPTH() argument
4044 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; in A4XX_TEX_CONST_3_DEPTH()
4050 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) in A4XX_TEX_CONST_4_LAYERSZ() argument
4052 assert(!(val & 0xfff)); in A4XX_TEX_CONST_4_LAYERSZ()
4053 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; in A4XX_TEX_CONST_4_LAYERSZ()
4057 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) in A4XX_TEX_CONST_4_BASE() argument
4059 assert(!(val & 0x1f)); in A4XX_TEX_CONST_4_BASE()
4060 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; in A4XX_TEX_CONST_4_BASE()