Lines Matching refs:val
272 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument
274 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF()
278 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument
280 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC()
284 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument
286 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK()
290 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument
292 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT()
298 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument
300 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; in CP_LOAD_STATE_1_STATE_TYPE()
304 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) in CP_LOAD_STATE_1_EXT_SRC_ADDR() argument
306 assert(!(val & 0x3)); in CP_LOAD_STATE_1_EXT_SRC_ADDR()
307 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; in CP_LOAD_STATE_1_EXT_SRC_ADDR()
313 static inline uint32_t CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(uint32_t val) in CP_LOAD_STATE_2_EXT_SRC_ADDR_HI() argument
315 return ((val) << CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK; in CP_LOAD_STATE_2_EXT_SRC_ADDR_HI()
321 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) in CP_DRAW_INDX_0_VIZ_QUERY() argument
323 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK; in CP_DRAW_INDX_0_VIZ_QUERY()
329 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) in CP_DRAW_INDX_1_PRIM_TYPE() argument
331 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK; in CP_DRAW_INDX_1_PRIM_TYPE()
335 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) in CP_DRAW_INDX_1_SOURCE_SELECT() argument
337 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK; in CP_DRAW_INDX_1_SOURCE_SELECT()
341 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) in CP_DRAW_INDX_1_VIS_CULL() argument
343 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK; in CP_DRAW_INDX_1_VIS_CULL()
347 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) in CP_DRAW_INDX_1_INDEX_SIZE() argument
349 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK; in CP_DRAW_INDX_1_INDEX_SIZE()
356 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) in CP_DRAW_INDX_1_NUM_INSTANCES() argument
358 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK; in CP_DRAW_INDX_1_NUM_INSTANCES()
364 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) in CP_DRAW_INDX_2_NUM_INDICES() argument
366 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK; in CP_DRAW_INDX_2_NUM_INDICES()
372 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) in CP_DRAW_INDX_3_INDX_BASE() argument
374 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK; in CP_DRAW_INDX_3_INDX_BASE()
380 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) in CP_DRAW_INDX_4_INDX_SIZE() argument
382 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK; in CP_DRAW_INDX_4_INDX_SIZE()
388 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) in CP_DRAW_INDX_2_0_VIZ_QUERY() argument
390 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK; in CP_DRAW_INDX_2_0_VIZ_QUERY()
396 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) in CP_DRAW_INDX_2_1_PRIM_TYPE() argument
398 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK; in CP_DRAW_INDX_2_1_PRIM_TYPE()
402 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) in CP_DRAW_INDX_2_1_SOURCE_SELECT() argument
404 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK; in CP_DRAW_INDX_2_1_SOURCE_SELECT()
408 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) in CP_DRAW_INDX_2_1_VIS_CULL() argument
410 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK; in CP_DRAW_INDX_2_1_VIS_CULL()
414 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) in CP_DRAW_INDX_2_1_INDEX_SIZE() argument
416 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK; in CP_DRAW_INDX_2_1_INDEX_SIZE()
423 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) in CP_DRAW_INDX_2_1_NUM_INSTANCES() argument
425 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK; in CP_DRAW_INDX_2_1_NUM_INSTANCES()
431 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) in CP_DRAW_INDX_2_2_NUM_INDICES() argument
433 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK; in CP_DRAW_INDX_2_2_NUM_INDICES()
439 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) in CP_DRAW_INDX_OFFSET_0_PRIM_TYPE() argument
441 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK; in CP_DRAW_INDX_OFFSET_0_PRIM_TYPE()
445 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) in CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT() argument
447 …return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT… in CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT()
451 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) in CP_DRAW_INDX_OFFSET_0_VIS_CULL() argument
453 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; in CP_DRAW_INDX_OFFSET_0_VIS_CULL()
457 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) in CP_DRAW_INDX_OFFSET_0_INDEX_SIZE() argument
459 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; in CP_DRAW_INDX_OFFSET_0_INDEX_SIZE()
463 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val) in CP_DRAW_INDX_OFFSET_0_TESS_MODE() argument
465 return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK; in CP_DRAW_INDX_OFFSET_0_TESS_MODE()
471 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) in CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES() argument
473 …return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES… in CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES()
479 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) in CP_DRAW_INDX_OFFSET_2_NUM_INDICES() argument
481 …return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MA… in CP_DRAW_INDX_OFFSET_2_NUM_INDICES()
489 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) in CP_DRAW_INDX_OFFSET_4_INDX_BASE() argument
491 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; in CP_DRAW_INDX_OFFSET_4_INDX_BASE()
497 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) in CP_DRAW_INDX_OFFSET_5_INDX_SIZE() argument
499 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; in CP_DRAW_INDX_OFFSET_5_INDX_SIZE()
507 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val) in CP_SET_DRAW_STATE__0_COUNT() argument
509 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK; in CP_SET_DRAW_STATE__0_COUNT()
517 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) in CP_SET_DRAW_STATE__0_GROUP_ID() argument
519 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK; in CP_SET_DRAW_STATE__0_GROUP_ID()
525 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) in CP_SET_DRAW_STATE__1_ADDR_LO() argument
527 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK; in CP_SET_DRAW_STATE__1_ADDR_LO()
533 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) in CP_SET_DRAW_STATE__2_ADDR_HI() argument
535 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK; in CP_SET_DRAW_STATE__2_ADDR_HI()
543 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) in CP_SET_BIN_1_X1() argument
545 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; in CP_SET_BIN_1_X1()
549 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) in CP_SET_BIN_1_Y1() argument
551 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; in CP_SET_BIN_1_Y1()
557 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) in CP_SET_BIN_2_X2() argument
559 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; in CP_SET_BIN_2_X2()
563 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) in CP_SET_BIN_2_Y2() argument
565 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; in CP_SET_BIN_2_Y2()
571 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) in CP_SET_BIN_DATA_0_BIN_DATA_ADDR() argument
573 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK; in CP_SET_BIN_DATA_0_BIN_DATA_ADDR()
579 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) in CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS() argument
581 …return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__… in CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS()
587 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val) in CP_REG_TO_MEM_0_REG() argument
589 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK; in CP_REG_TO_MEM_0_REG()
593 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val) in CP_REG_TO_MEM_0_CNT() argument
595 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK; in CP_REG_TO_MEM_0_CNT()
603 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val) in CP_REG_TO_MEM_1_DEST() argument
605 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK; in CP_REG_TO_MEM_1_DEST()
613 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val) in CP_DISPATCH_COMPUTE_1_X() argument
615 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK; in CP_DISPATCH_COMPUTE_1_X()
621 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val) in CP_DISPATCH_COMPUTE_2_Y() argument
623 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK; in CP_DISPATCH_COMPUTE_2_Y()
629 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val) in CP_DISPATCH_COMPUTE_3_Z() argument
631 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK; in CP_DISPATCH_COMPUTE_3_Z()
637 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) in CP_SET_RENDER_MODE_0_MODE() argument
639 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK; in CP_SET_RENDER_MODE_0_MODE()
645 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) in CP_SET_RENDER_MODE_1_ADDR_0_LO() argument
647 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK; in CP_SET_RENDER_MODE_1_ADDR_0_LO()
653 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) in CP_SET_RENDER_MODE_2_ADDR_0_HI() argument
655 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK; in CP_SET_RENDER_MODE_2_ADDR_0_HI()
666 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) in CP_SET_RENDER_MODE_5_ADDR_1_LEN() argument
668 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK; in CP_SET_RENDER_MODE_5_ADDR_1_LEN()
674 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) in CP_SET_RENDER_MODE_6_ADDR_1_LO() argument
676 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK; in CP_SET_RENDER_MODE_6_ADDR_1_LO()
682 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) in CP_SET_RENDER_MODE_7_ADDR_1_HI() argument
684 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK; in CP_SET_RENDER_MODE_7_ADDR_1_HI()
692 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) in CP_PERFCOUNTER_ACTION_1_ADDR_0_LO() argument
694 …return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MA… in CP_PERFCOUNTER_ACTION_1_ADDR_0_LO()
700 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) in CP_PERFCOUNTER_ACTION_2_ADDR_0_HI() argument
702 …return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MA… in CP_PERFCOUNTER_ACTION_2_ADDR_0_HI()
708 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) in CP_EVENT_WRITE_0_EVENT() argument
710 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK; in CP_EVENT_WRITE_0_EVENT()
716 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) in CP_EVENT_WRITE_1_ADDR_0_LO() argument
718 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK; in CP_EVENT_WRITE_1_ADDR_0_LO()
724 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) in CP_EVENT_WRITE_2_ADDR_0_HI() argument
726 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK; in CP_EVENT_WRITE_2_ADDR_0_HI()
734 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val) in CP_BLIT_0_OP() argument
736 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK; in CP_BLIT_0_OP()
742 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val) in CP_BLIT_1_SRC_X1() argument
744 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK; in CP_BLIT_1_SRC_X1()
748 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val) in CP_BLIT_1_SRC_Y1() argument
750 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK; in CP_BLIT_1_SRC_Y1()
756 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val) in CP_BLIT_2_SRC_X2() argument
758 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK; in CP_BLIT_2_SRC_X2()
762 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val) in CP_BLIT_2_SRC_Y2() argument
764 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK; in CP_BLIT_2_SRC_Y2()
770 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val) in CP_BLIT_3_DST_X1() argument
772 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK; in CP_BLIT_3_DST_X1()
776 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val) in CP_BLIT_3_DST_Y1() argument
778 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK; in CP_BLIT_3_DST_Y1()
784 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val) in CP_BLIT_4_DST_X2() argument
786 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK; in CP_BLIT_4_DST_X2()
790 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val) in CP_BLIT_4_DST_Y2() argument
792 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK; in CP_BLIT_4_DST_Y2()