37 static void r300_apply_hyperz_blacklist(struct r300_capabilities* caps)  in r300_apply_hyperz_blacklist()  argument
58             caps->zmask_ram = 0;  in r300_apply_hyperz_blacklist()
59             caps->hiz_ram = 0;  in r300_apply_hyperz_blacklist()
66 void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)  in r300_parse_chipset()  argument
71             caps->family = CHIP_##chipfamily; \  in r300_parse_chipset()
83     caps->high_second_pipe = FALSE;  in r300_parse_chipset()
84     caps->num_vert_fpus = 0;  in r300_parse_chipset()
85     caps->hiz_ram = 0;  in r300_parse_chipset()
86     caps->zmask_ram = 0;  in r300_parse_chipset()
87     caps->has_cmask = FALSE;  in r300_parse_chipset()
90     switch (caps->family) {  in r300_parse_chipset()
93         caps->high_second_pipe = TRUE;  in r300_parse_chipset()
94         caps->num_vert_fpus = 4;  in r300_parse_chipset()
95         caps->has_cmask = TRUE; /* guessed because there is also HiZ */  in r300_parse_chipset()
96         caps->hiz_ram = R300_HIZ_LIMIT;  in r300_parse_chipset()
97         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
102         caps->high_second_pipe = TRUE;  in r300_parse_chipset()
103         caps->num_vert_fpus = 2;  in r300_parse_chipset()
104         caps->zmask_ram = RV3xx_ZMASK_SIZE;  in r300_parse_chipset()
108         caps->high_second_pipe = TRUE;  in r300_parse_chipset()
109         caps->num_vert_fpus = 2;  in r300_parse_chipset()
110         caps->has_cmask = TRUE; /* guessed because there is also HiZ */  in r300_parse_chipset()
111         caps->hiz_ram = R300_HIZ_LIMIT;  in r300_parse_chipset()
112         caps->zmask_ram = RV3xx_ZMASK_SIZE;  in r300_parse_chipset()
123         caps->zmask_ram = RV3xx_ZMASK_SIZE;  in r300_parse_chipset()
132         caps->num_vert_fpus = 6;  in r300_parse_chipset()
133         caps->has_cmask = TRUE; /* guessed because there is also HiZ */  in r300_parse_chipset()
134         caps->hiz_ram = R300_HIZ_LIMIT;  in r300_parse_chipset()
135         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
139         caps->num_vert_fpus = 8;  in r300_parse_chipset()
140         caps->has_cmask = TRUE;  in r300_parse_chipset()
141         caps->hiz_ram = R300_HIZ_LIMIT;  in r300_parse_chipset()
142         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
146         caps->num_vert_fpus = 2;  in r300_parse_chipset()
147         caps->has_cmask = TRUE;  in r300_parse_chipset()
148         caps->hiz_ram = R300_HIZ_LIMIT;  in r300_parse_chipset()
149         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
153         caps->num_vert_fpus = 5;  in r300_parse_chipset()
154         caps->has_cmask = TRUE;  in r300_parse_chipset()
155         caps->hiz_ram = RV530_HIZ_LIMIT;  in r300_parse_chipset()
156         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
162         caps->num_vert_fpus = 8;  in r300_parse_chipset()
163         caps->has_cmask = TRUE;  in r300_parse_chipset()
164         caps->hiz_ram = RV530_HIZ_LIMIT;  in r300_parse_chipset()
165         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
169     caps->num_tex_units = 16;  in r300_parse_chipset()
170     caps->is_r400 = caps->family >= CHIP_R420 && caps->family < CHIP_RV515;  in r300_parse_chipset()
171     caps->is_r500 = caps->family >= CHIP_RV515;  in r300_parse_chipset()
172     caps->is_rv350 = caps->family >= CHIP_RV350;  in r300_parse_chipset()
173     caps->z_compress = caps->is_rv350 ? R300_ZCOMP_8X8 : R300_ZCOMP_4X4;  in r300_parse_chipset()
174     caps->dxtc_swizzle = caps->is_r400 || caps->is_r500;  in r300_parse_chipset()
175     caps->has_us_format = caps->family == CHIP_R520;  in r300_parse_chipset()
176     caps->has_tcl = caps->num_vert_fpus > 0;  in r300_parse_chipset()
178     if (caps->has_tcl) {  in r300_parse_chipset()
179         caps->has_tcl = debug_get_bool_option("RADEON_NO_TCL", FALSE) ? FALSE : TRUE;  in r300_parse_chipset()
182     r300_apply_hyperz_blacklist(caps);  in r300_parse_chipset()