131     unsigned Cascade;  member
133     RegInfo() : Stage(RS_New), Cascade(0) {}  in RegInfo()
530   unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;  in canEvictInterference()  local
531   if (!Cascade)  in canEvictInterference()
532     Cascade = NextCascade;  in canEvictInterference()
554       unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;  in canEvictInterference()
555       if (Cascade <= IntfCascade) {  in canEvictInterference()
587   unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;  in evictInterference()  local
588   if (!Cascade)  in evictInterference()
589     Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;  in evictInterference()
592                << " interference: Cascade " << Cascade << '\n');  in evictInterference()
599       assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||  in evictInterference()
602       ExtraRegInfo[Intf->reg].Cascade = Cascade;  in evictInterference()
1563                << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');  in selectOrSplit()