Lines Matching refs:MISC
550 #define MISC(str, type) if (name == str) SET(type); macro
632 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ? in ARMFlagFromOpName()
633 MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ? in ARMFlagFromOpName()
634 MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ? in ARMFlagFromOpName()
635 MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ? in ARMFlagFromOpName()
636 MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ? in ARMFlagFromOpName()
637 MISC("bltarget", "kOperandTypeARMBranchTarget"); // ? in ARMFlagFromOpName()
639 MISC("br_target", "kOperandTypeARMBranchTarget"); // ? in ARMFlagFromOpName()
640 MISC("bl_target", "kOperandTypeARMBranchTarget"); // ? in ARMFlagFromOpName()
641 MISC("blx_target", "kOperandTypeARMBranchTarget"); // ? in ARMFlagFromOpName()
643 MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ? in ARMFlagFromOpName()
644 MISC("t_blxtarget", "kOperandTypeARMBranchTarget"); // ? in ARMFlagFromOpName()
645 MISC("so_reg_imm", "kOperandTypeARMSoRegReg"); // R, R, I in ARMFlagFromOpName()
646 MISC("so_reg_reg", "kOperandTypeARMSoRegImm"); // R, R, I in ARMFlagFromOpName()
647 MISC("shift_so_reg_reg", "kOperandTypeARMSoRegReg"); // R, R, I in ARMFlagFromOpName()
648 MISC("shift_so_reg_imm", "kOperandTypeARMSoRegImm"); // R, R, I in ARMFlagFromOpName()
649 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I in ARMFlagFromOpName()
650 MISC("so_imm", "kOperandTypeARMSoImm"); // I in ARMFlagFromOpName()
651 MISC("rot_imm", "kOperandTypeARMRotImm"); // I in ARMFlagFromOpName()
652 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I in ARMFlagFromOpName()
653 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I in ARMFlagFromOpName()
654 MISC("pred", "kOperandTypeARMPredicate"); // I, R in ARMFlagFromOpName()
655 MISC("it_pred", "kOperandTypeARMPredicate"); // I in ARMFlagFromOpName()
656 MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I in ARMFlagFromOpName()
657 MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I in ARMFlagFromOpName()
658 MISC("postidx_reg", "kOperandTypeARMAddrMode3Offset"); // R, I in ARMFlagFromOpName()
659 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I in ARMFlagFromOpName()
660 MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I in ARMFlagFromOpName()
661 MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I in ARMFlagFromOpName()
662 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I in ARMFlagFromOpName()
663 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I in ARMFlagFromOpName()
664 MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I in ARMFlagFromOpName()
665 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I in ARMFlagFromOpName()
666 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I in ARMFlagFromOpName()
667 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I in ARMFlagFromOpName()
668 MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I in ARMFlagFromOpName()
669 MISC("addrmode6oneL32", "kOperandTypeARMAddrMode6"); // R, R, I, I in ARMFlagFromOpName()
670 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I in ARMFlagFromOpName()
671 MISC("addr_offset_none", "kOperandTypeARMAddrMode7"); // R in ARMFlagFromOpName()
672 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ... in ARMFlagFromOpName()
673 MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ... in ARMFlagFromOpName()
674 MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ... in ARMFlagFromOpName()
675 MISC("it_mask", "kOperandTypeThumbITMask"); // I in ARMFlagFromOpName()
676 MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg"); // R in ARMFlagFromOpName()
677 MISC("t2addrmode_posimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I in ARMFlagFromOpName()
678 MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I in ARMFlagFromOpName()
679 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I in ARMFlagFromOpName()
680 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I in ARMFlagFromOpName()
681 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I in ARMFlagFromOpName()
682 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I in ARMFlagFromOpName()
683 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I in ARMFlagFromOpName()
684 MISC("t2addrmode_imm0_1020s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I in ARMFlagFromOpName()
685 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset"); in ARMFlagFromOpName()
687 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I in ARMFlagFromOpName()
688 MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS1"); // R, R in ARMFlagFromOpName()
689 MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS2"); // R, R in ARMFlagFromOpName()
690 MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS4"); // R, R in ARMFlagFromOpName()
691 MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS1"); // R, I in ARMFlagFromOpName()
692 MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS2"); // R, I in ARMFlagFromOpName()
693 MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS4"); // R, I in ARMFlagFromOpName()
694 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R in ARMFlagFromOpName()
695 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I in ARMFlagFromOpName()
696 MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I in ARMFlagFromOpName()
697 MISC("addrmode_tbb", "kOperandTypeThumbAddrModeRR"); // R, R in ARMFlagFromOpName()
698 MISC("addrmode_tbh", "kOperandTypeThumbAddrModeRR"); // R, R in ARMFlagFromOpName()
705 #undef MISC