1353 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)  in load_cpu_fw()  argument
1359 	val = REG_RD_IND(bp, cpu_reg->mode);  in load_cpu_fw()
1360 	val |= cpu_reg->mode_value_halt;  in load_cpu_fw()
1361 	REG_WR_IND(bp, cpu_reg->mode, val);  in load_cpu_fw()
1362 	REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
1365 	offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);  in load_cpu_fw()
1375 	offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);  in load_cpu_fw()
1385 	offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);  in load_cpu_fw()
1395 	offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);  in load_cpu_fw()
1405 	offset = cpu_reg->spad_base +  in load_cpu_fw()
1406 		(fw->rodata_addr - cpu_reg->mips_view_base);  in load_cpu_fw()
1416 	REG_WR_IND(bp, cpu_reg->inst, 0);  in load_cpu_fw()
1417 	REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);  in load_cpu_fw()
1420 	val = REG_RD_IND(bp, cpu_reg->mode);  in load_cpu_fw()
1421 	val &= ~cpu_reg->mode_value_halt;  in load_cpu_fw()
1422 	REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
1423 	REG_WR_IND(bp, cpu_reg->mode, val);  in load_cpu_fw()
1429 	struct cpu_reg cpu_reg;  in bnx2_init_cpus()  local
1442 	cpu_reg.mode = BNX2_RXP_CPU_MODE;  in bnx2_init_cpus()
1443 	cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;  in bnx2_init_cpus()
1444 	cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;  in bnx2_init_cpus()
1445 	cpu_reg.state = BNX2_RXP_CPU_STATE;  in bnx2_init_cpus()
1446 	cpu_reg.state_value_clear = 0xffffff;  in bnx2_init_cpus()
1447 	cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;  in bnx2_init_cpus()
1448 	cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;  in bnx2_init_cpus()
1449 	cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;  in bnx2_init_cpus()
1450 	cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;  in bnx2_init_cpus()
1451 	cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;  in bnx2_init_cpus()
1452 	cpu_reg.spad_base = BNX2_RXP_SCRATCH;  in bnx2_init_cpus()
1453 	cpu_reg.mips_view_base = 0x8000000;  in bnx2_init_cpus()
1485 	load_cpu_fw(bp, &cpu_reg, &fw);  in bnx2_init_cpus()
1488 	cpu_reg.mode = BNX2_TXP_CPU_MODE;  in bnx2_init_cpus()
1489 	cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;  in bnx2_init_cpus()
1490 	cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;  in bnx2_init_cpus()
1491 	cpu_reg.state = BNX2_TXP_CPU_STATE;  in bnx2_init_cpus()
1492 	cpu_reg.state_value_clear = 0xffffff;  in bnx2_init_cpus()
1493 	cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;  in bnx2_init_cpus()
1494 	cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;  in bnx2_init_cpus()
1495 	cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;  in bnx2_init_cpus()
1496 	cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;  in bnx2_init_cpus()
1497 	cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;  in bnx2_init_cpus()
1498 	cpu_reg.spad_base = BNX2_TXP_SCRATCH;  in bnx2_init_cpus()
1499 	cpu_reg.mips_view_base = 0x8000000;  in bnx2_init_cpus()
1531 	load_cpu_fw(bp, &cpu_reg, &fw);  in bnx2_init_cpus()
1534 	cpu_reg.mode = BNX2_TPAT_CPU_MODE;  in bnx2_init_cpus()
1535 	cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;  in bnx2_init_cpus()
1536 	cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;  in bnx2_init_cpus()
1537 	cpu_reg.state = BNX2_TPAT_CPU_STATE;  in bnx2_init_cpus()
1538 	cpu_reg.state_value_clear = 0xffffff;  in bnx2_init_cpus()
1539 	cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;  in bnx2_init_cpus()
1540 	cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;  in bnx2_init_cpus()
1541 	cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;  in bnx2_init_cpus()
1542 	cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;  in bnx2_init_cpus()
1543 	cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;  in bnx2_init_cpus()
1544 	cpu_reg.spad_base = BNX2_TPAT_SCRATCH;  in bnx2_init_cpus()
1545 	cpu_reg.mips_view_base = 0x8000000;  in bnx2_init_cpus()
1577 	load_cpu_fw(bp, &cpu_reg, &fw);  in bnx2_init_cpus()
1580 	cpu_reg.mode = BNX2_COM_CPU_MODE;  in bnx2_init_cpus()
1581 	cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;  in bnx2_init_cpus()
1582 	cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;  in bnx2_init_cpus()
1583 	cpu_reg.state = BNX2_COM_CPU_STATE;  in bnx2_init_cpus()
1584 	cpu_reg.state_value_clear = 0xffffff;  in bnx2_init_cpus()
1585 	cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;  in bnx2_init_cpus()
1586 	cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;  in bnx2_init_cpus()
1587 	cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;  in bnx2_init_cpus()
1588 	cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;  in bnx2_init_cpus()
1589 	cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;  in bnx2_init_cpus()
1590 	cpu_reg.spad_base = BNX2_COM_SCRATCH;  in bnx2_init_cpus()
1591 	cpu_reg.mips_view_base = 0x8000000;  in bnx2_init_cpus()
1623 	load_cpu_fw(bp, &cpu_reg, &fw);  in bnx2_init_cpus()