Lines Matching refs:REG_OPER_OP_ORDER
18 REG_OPER_OP_ORDER, enumerator
33 {0x01, "add", OPER_REG_OP_ORDER}, {0x03, "add", REG_OPER_OP_ORDER},
34 {0x09, "or", OPER_REG_OP_ORDER}, {0x0B, "or", REG_OPER_OP_ORDER},
35 {0x13, "adc", REG_OPER_OP_ORDER}, {0x1B, "sbb", REG_OPER_OP_ORDER},
36 {0x21, "and", OPER_REG_OP_ORDER}, {0x23, "and", REG_OPER_OP_ORDER},
37 {0x29, "sub", OPER_REG_OP_ORDER}, {0x2A, "subb", REG_OPER_OP_ORDER},
38 {0x2B, "sub", REG_OPER_OP_ORDER}, {0x31, "xor", OPER_REG_OP_ORDER},
39 {0x33, "xor", REG_OPER_OP_ORDER}, {0x38, "cmpb", OPER_REG_OP_ORDER},
40 {0x39, "cmp", OPER_REG_OP_ORDER}, {0x3A, "cmpb", REG_OPER_OP_ORDER},
41 {0x3B, "cmp", REG_OPER_OP_ORDER}, {0x84, "test_b", REG_OPER_OP_ORDER},
42 {0x85, "test", REG_OPER_OP_ORDER}, {0x86, "xchg_b", REG_OPER_OP_ORDER},
43 {0x87, "xchg", REG_OPER_OP_ORDER}, {0x8A, "mov_b", REG_OPER_OP_ORDER},
44 {0x8B, "mov", REG_OPER_OP_ORDER}, {0x8D, "lea", REG_OPER_OP_ORDER},
530 case REG_OPER_OP_ORDER: { in PrintOperands()
727 int op_size = PrintOperands(mnem, REG_OPER_OP_ORDER, data + 2); in CMov()
1351 data += PrintOperands("imul", REG_OPER_OP_ORDER, data); in InstructionDecode()
1358 data += PrintOperands("imul", REG_OPER_OP_ORDER, data); in InstructionDecode()
1493 data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data); in InstructionDecode()
1644 data += PrintOperands("cmpw", REG_OPER_OP_ORDER, data); in InstructionDecode()
1667 data += PrintOperands("mov_w", REG_OPER_OP_ORDER, data); in InstructionDecode()