Lines Matching refs:BITS3
196 #define BITS3(_b2,_b1,_b0) \ macro
3120 case BITS3(0,0,0): // UXTB in dis_ARM64_data_processing_register()
3122 case BITS3(0,0,1): // UXTH in dis_ARM64_data_processing_register()
3124 case BITS3(0,1,0): // UXTW -- noop for the 32bit case in dis_ARM64_data_processing_register()
3129 case BITS3(0,1,1): // UXTX -- always a noop in dis_ARM64_data_processing_register()
3131 case BITS3(1,0,0): // SXTB in dis_ARM64_data_processing_register()
3133 case BITS3(1,0,1): // SXTH in dis_ARM64_data_processing_register()
3135 case BITS3(1,1,0): // SXTW -- noop for the 32bit case in dis_ARM64_data_processing_register()
3140 case BITS3(1,1,1): // SXTX -- always a noop in dis_ARM64_data_processing_register()
3512 && INSN(15,13) == BITS3(0,1,0)) { in dis_ARM64_data_processing_register()
4579 case BITS3(0,0,0): break; // 8 bit, valid for both int and vec in gen_indexed_EA()
4580 case BITS3(0,0,1): break; // 16 bit, valid for both int and vec in gen_indexed_EA()
4581 case BITS3(0,1,0): break; // 32 bit, valid for both int and vec in gen_indexed_EA()
4582 case BITS3(0,1,1): break; // 64 bit, valid for both int and vec in gen_indexed_EA()
4583 case BITS3(1,0,0): // can only ever be valid for the vector case in gen_indexed_EA()
4585 case BITS3(1,0,1): // these sizes are never valid in gen_indexed_EA()
4586 case BITS3(1,1,0): in gen_indexed_EA()
4587 case BITS3(1,1,1): goto fail; in gen_indexed_EA()
5172 case BITS3(1,0,0): in dis_ARM64_load_store()
5173 case BITS3(0,1,0): case BITS3(0,1,1): in dis_ARM64_load_store()
5174 case BITS3(0,0,0): case BITS3(0,0,1): in dis_ARM64_load_store()
5242 case BITS3(1,0,0): // LDRSW Xt in dis_ARM64_load_store()
5243 case BITS3(0,1,0): case BITS3(0,1,1): // LDRSH Xt, Wt in dis_ARM64_load_store()
5244 case BITS3(0,0,0): case BITS3(0,0,1): // LDRSB Xt, Wt in dis_ARM64_load_store()
5320 case BITS3(1,0,0): // LDURSW Xt in dis_ARM64_load_store()
5321 case BITS3(0,1,0): case BITS3(0,1,1): // LDURSH Xt, Wt in dis_ARM64_load_store()
5322 case BITS3(0,0,0): case BITS3(0,0,1): // LDURSB Xt, Wt in dis_ARM64_load_store()
6493 && (INSN(23,21) & BITS3(1,0,1)) == BITS3(0,0,0) in dis_ARM64_load_store()
7146 && INSN(23,21) == BITS3(0,0,1) && INSN(4,0) == BITS5(0,0,0,0,0)) { in dis_ARM64_branch_etc()
8666 if (opcode == BITS3(0,0,1) || opcode == BITS3(1,0,1)) { in dis_AdvSIMD_ZIP_UZP_TRN()
8670 Bool isUZP1 = opcode == BITS3(0,0,1); in dis_AdvSIMD_ZIP_UZP_TRN()
8693 if (opcode == BITS3(0,1,0) || opcode == BITS3(1,1,0)) { in dis_AdvSIMD_ZIP_UZP_TRN()
8697 Bool isTRN1 = opcode == BITS3(0,1,0); in dis_AdvSIMD_ZIP_UZP_TRN()
8716 if (opcode == BITS3(0,1,1) || opcode == BITS3(1,1,1)) { in dis_AdvSIMD_ZIP_UZP_TRN()
8720 Bool isZIP1 = opcode == BITS3(0,1,1); in dis_AdvSIMD_ZIP_UZP_TRN()
13227 if (sz == BITS2(0,0) && opc <= BITS3(1,1,0)) { in dis_AdvSIMD_crypto_three_reg_sha()
13272 case BITS3(0,0,0): case BITS3(0,0,1): case BITS3(0,1,0): in dis_AdvSIMD_crypto_three_reg_sha()
13276 case BITS3(0,1,1): case BITS3(1,0,0): in dis_AdvSIMD_crypto_three_reg_sha()
13277 case BITS3(1,0,1): case BITS3(1,1,0): in dis_AdvSIMD_crypto_three_reg_sha()
13294 case BITS3(0,0,0): case BITS3(0,0,1): case BITS3(0,1,0): in dis_AdvSIMD_crypto_three_reg_sha()
13297 case BITS3(0,1,1): case BITS3(1,1,0): in dis_AdvSIMD_crypto_three_reg_sha()
13300 case BITS3(1,0,0): case BITS3(1,0,1): in dis_AdvSIMD_crypto_three_reg_sha()
13747 case BITS3(0,1,1): ch = 'z'; irrmE = mkU32(Irrm_ZERO); break; in dis_AdvSIMD_fp_data_proc_1_source()
13748 case BITS3(0,1,0): ch = 'm'; irrmE = mkU32(Irrm_NegINF); break; in dis_AdvSIMD_fp_data_proc_1_source()
13749 case BITS3(0,0,1): ch = 'p'; irrmE = mkU32(Irrm_PosINF); break; in dis_AdvSIMD_fp_data_proc_1_source()
13751 case BITS3(1,0,0): ch = 'a'; irrmE = mkU32(Irrm_NEAREST); break; in dis_AdvSIMD_fp_data_proc_1_source()
13754 case BITS3(1,1,0): in dis_AdvSIMD_fp_data_proc_1_source()
13756 case BITS3(1,1,1): in dis_AdvSIMD_fp_data_proc_1_source()
13760 case BITS3(0,0,0): ch = 'n'; irrmE = mkU32(Irrm_NEAREST); break; in dis_AdvSIMD_fp_data_proc_1_source()
13947 || INSN(21,21) != 1 || INSN(12,10) != BITS3(1,0,0)) { in dis_AdvSIMD_fp_immediate()
13999 && (op == BITS3(0,0,0) || op == BITS3(0,0,1))) { in dis_AdvSIMD_fp_to_from_fixedp_conv()
14059 && (op == BITS3(0,1,0) || op == BITS3(0,1,1)) in dis_AdvSIMD_fp_to_from_fixedp_conv()
14134 && ( ((op == BITS3(0,0,0) || op == BITS3(0,0,1)) && True) in dis_AdvSIMD_fp_to_from_int_conv()
14135 || ((op == BITS3(1,0,0) || op == BITS3(1,0,1)) && rm == BITS2(0,0)) in dis_AdvSIMD_fp_to_from_int_conv()
14144 if (op == BITS3(0,0,0) || op == BITS3(0,0,1)) { in dis_AdvSIMD_fp_to_from_int_conv()
14153 vassert(op == BITS3(1,0,0) || op == BITS3(1,0,1)); in dis_AdvSIMD_fp_to_from_int_conv()
14251 if (ty <= X01 && rm == X00 && (op == BITS3(0,1,0) || op == BITS3(0,1,1))) { in dis_AdvSIMD_fp_to_from_int_conv()
14286 if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,1)) in dis_AdvSIMD_fp_to_from_int_conv()
14289 if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,0)) in dis_AdvSIMD_fp_to_from_int_conv()
14293 if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,1)) in dis_AdvSIMD_fp_to_from_int_conv()
14296 if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,0)) in dis_AdvSIMD_fp_to_from_int_conv()
14299 if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,1)) in dis_AdvSIMD_fp_to_from_int_conv()
14302 if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,0)) in dis_AdvSIMD_fp_to_from_int_conv()