Lines Matching refs:bitQ
2175 static IRExpr* math_MAYBE_ZERO_HI64 ( UInt bitQ, IRTemp fullWidth ) in math_MAYBE_ZERO_HI64() argument
2177 if (bitQ == 1) return mkexpr(fullWidth); in math_MAYBE_ZERO_HI64()
2178 if (bitQ == 0) return unop(Iop_ZeroHI64ofV128, mkexpr(fullWidth)); in math_MAYBE_ZERO_HI64()
2183 static IRExpr* math_MAYBE_ZERO_HI64_fromE ( UInt bitQ, IRExpr* fullWidth ) in math_MAYBE_ZERO_HI64_fromE() argument
2187 return math_MAYBE_ZERO_HI64(bitQ, fullWidthT); in math_MAYBE_ZERO_HI64_fromE()
4697 const HChar* nameArr_Q_SZ ( UInt bitQ, UInt size ) in nameArr_Q_SZ() argument
4699 vassert(bitQ <= 1 && size <= 3); in nameArr_Q_SZ()
4702 UInt ix = (bitQ << 2) | size; in nameArr_Q_SZ()
5820 Bool bitQ = INSN(30,30); in dis_ARM64_load_store() local
5828 Bool isQ = bitQ == 1; in dis_ARM64_load_store()
5973 math_MAYBE_ZERO_HI64(bitQ, u3)); in dis_ARM64_load_store()
5976 math_MAYBE_ZERO_HI64(bitQ, u2)); in dis_ARM64_load_store()
5979 math_MAYBE_ZERO_HI64(bitQ, u1)); in dis_ARM64_load_store()
5982 math_MAYBE_ZERO_HI64(bitQ, u0)); in dis_ARM64_load_store()
6003 const HChar* arr = nameArr_Q_SZ(bitQ, sz); in dis_ARM64_load_store()
6034 Bool bitQ = INSN(30,30); in dis_ARM64_load_store() local
6042 Bool isQ = bitQ == 1; in dis_ARM64_load_store()
6151 math_MAYBE_ZERO_HI64(bitQ, u3)); in dis_ARM64_load_store()
6154 math_MAYBE_ZERO_HI64(bitQ, u2)); in dis_ARM64_load_store()
6157 math_MAYBE_ZERO_HI64(bitQ, u1)); in dis_ARM64_load_store()
6159 math_MAYBE_ZERO_HI64(bitQ, u0)); in dis_ARM64_load_store()
6180 const HChar* arr = nameArr_Q_SZ(bitQ, sz); in dis_ARM64_load_store()
6213 UInt bitQ = INSN(30,30); in dis_ARM64_load_store() local
6256 putQReg128((tt+3) % 32, math_MAYBE_ZERO_HI64(bitQ, v3)); in dis_ARM64_load_store()
6263 putQReg128((tt+2) % 32, math_MAYBE_ZERO_HI64(bitQ, v2)); in dis_ARM64_load_store()
6270 putQReg128((tt+1) % 32, math_MAYBE_ZERO_HI64(bitQ, v1)); in dis_ARM64_load_store()
6277 putQReg128((tt+0) % 32, math_MAYBE_ZERO_HI64(bitQ, v0)); in dis_ARM64_load_store()
6291 const HChar* arr = nameArr_Q_SZ(bitQ, sz); in dis_ARM64_load_store()
6328 UInt bitQ = INSN(30,30); in dis_ARM64_load_store() local
6348 UInt xx_q_S_sz = (xx << 4) | (bitQ << 3) | (bitS << 2) | sz; in dis_ARM64_load_store()
6447 const HChar* arr = nameArr_Q_SZ(bitQ, sz); in dis_ARM64_load_store()
7436 Bool bitQ, Bool bitSZ ) in getLaneInfo_Q_SZ() argument
7438 vassert(bitQ == True || bitQ == False); in getLaneInfo_Q_SZ()
7440 if (bitQ && bitSZ) { // 2x64 in getLaneInfo_Q_SZ()
7448 if (bitQ && !bitSZ) { // 4x32 in getLaneInfo_Q_SZ()
7456 if (!bitQ && !bitSZ) { // 2x32 in getLaneInfo_Q_SZ()
8469 IRTemp vecM, IRTemp vecN, Bool isD, UInt bitQ in math_REARRANGE_FOR_FLOATING_PAIRWISE() argument
8478 vassert(bitQ == 1); in math_REARRANGE_FOR_FLOATING_PAIRWISE()
8482 else if (!isD && bitQ == 1) { in math_REARRANGE_FOR_FLOATING_PAIRWISE()
8488 vassert(!isD && bitQ == 0); in math_REARRANGE_FOR_FLOATING_PAIRWISE()
8538 UInt bitQ = INSN(30,30); in dis_AdvSIMD_EXT() local
8552 if (bitQ == 1) { in dis_AdvSIMD_EXT()
8600 UInt bitQ = INSN(30,30); in dis_AdvSIMD_TBL_TBX() local
8632 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_TBL_TBX()
8633 const HChar* Ta = bitQ ==1 ? "16b" : "8b"; in dis_AdvSIMD_TBL_TBX()
8659 UInt bitQ = INSN(30,30); in dis_AdvSIMD_ZIP_UZP_TRN() local
8669 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_ZIP_UZP_TRN()
8676 if (bitQ == 0) { in dis_AdvSIMD_ZIP_UZP_TRN()
8685 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_ZIP_UZP_TRN()
8687 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_ZIP_UZP_TRN()
8696 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_ZIP_UZP_TRN()
8708 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_ZIP_UZP_TRN()
8710 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_ZIP_UZP_TRN()
8719 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_ZIP_UZP_TRN()
8726 if (bitQ == 0 && !isZIP1) { in dis_AdvSIMD_ZIP_UZP_TRN()
8741 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_ZIP_UZP_TRN()
8743 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_ZIP_UZP_TRN()
8767 UInt bitQ = INSN(30,30); in dis_AdvSIMD_across_lanes() local
8778 if (size == X11 || (size == X10 && bitQ == 0)) return False; in dis_AdvSIMD_across_lanes()
8789 if (bitQ == 1) { in dis_AdvSIMD_across_lanes()
8802 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_across_lanes()
8822 if (size == X10 && bitQ == 0) return False; // 2s case not allowed in dis_AdvSIMD_across_lanes()
8853 assign(tN2, bitQ == 0 in dis_AdvSIMD_across_lanes()
8864 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_across_lanes()
8877 if (bitQ == 0) return False; // Only 4s is allowed in dis_AdvSIMD_across_lanes()
8909 UInt bitQ = INSN(30,30); in dis_AdvSIMD_copy() local
8928 if (bitQ == 0 && laneSzLg2 == X11) in dis_AdvSIMD_copy()
8930 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_copy()
8931 const HChar* arT = nameArr_Q_SZ(bitQ, laneSzLg2); in dis_AdvSIMD_copy()
8949 Bool isQ = bitQ == 1; in dis_AdvSIMD_copy()
8997 if (bitQ == 1 && bitOP == 0 && imm4 == BITS4(0,0,1,1)) { in dis_AdvSIMD_copy()
9066 if (!bitQ && (imm5 & 1)) { // 0:xxxx1 in dis_AdvSIMD_copy()
9073 else if (bitQ && (imm5 & 1)) { // 1:xxxx1 in dis_AdvSIMD_copy()
9080 else if (!bitQ && (imm5 & 2)) { // 0:xxx10 in dis_AdvSIMD_copy()
9087 else if (bitQ && (imm5 & 2)) { // 1:xxx10 in dis_AdvSIMD_copy()
9094 else if (!bitQ && (imm5 & 4)) { // 0:xx100 in dis_AdvSIMD_copy()
9101 else if (bitQ && (imm5 & 4)) { // 1:xxx10 in dis_AdvSIMD_copy()
9108 else if (bitQ && (imm5 & 8)) { // 1:x1000 in dis_AdvSIMD_copy()
9120 nameIRegOrZR(bitQ == 1, dd), in dis_AdvSIMD_copy()
9137 if (bitQ == 1 && bitOP == 1) { in dis_AdvSIMD_copy()
9198 UInt bitQ = INSN(30,30); in dis_AdvSIMD_modified_immediate() local
9290 ok = bitQ == 1; isFMOV = True; break; in dis_AdvSIMD_modified_immediate()
9309 if (bitQ == 0) { in dis_AdvSIMD_modified_immediate()
9320 ULong imm64hi = bitQ == 0 ? 0 : imm64lo; in dis_AdvSIMD_modified_immediate()
10683 UInt bitQ = INSN(30,30); in dis_AdvSIMD_shift_by_immediate() local
10705 Bool isQ = bitQ == 1; in dis_AdvSIMD_shift_by_immediate()
10709 if (!ok || (bitQ == 0 && size == X11)) return False; in dis_AdvSIMD_shift_by_immediate()
10729 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_shift_by_immediate()
10754 Bool isQ = bitQ == 1; in dis_AdvSIMD_shift_by_immediate()
10758 if (!ok || (bitQ == 0 && size == X11)) return False; in dis_AdvSIMD_shift_by_immediate()
10772 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_shift_by_immediate()
10794 Bool isQ = bitQ == 1; in dis_AdvSIMD_shift_by_immediate()
10796 if (!ok || (bitQ == 0 && size == X11)) return False; in dis_AdvSIMD_shift_by_immediate()
10814 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_shift_by_immediate()
10836 Bool isQ = bitQ == 1; in dis_AdvSIMD_shift_by_immediate()
10838 if (!ok || (bitQ == 0 && size == X11)) return False; in dis_AdvSIMD_shift_by_immediate()
10862 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_shift_by_immediate()
10879 Bool isQ = bitQ == 1; in dis_AdvSIMD_shift_by_immediate()
10881 if (!ok || (bitQ == 0 && size == X11)) return False; in dis_AdvSIMD_shift_by_immediate()
10899 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_shift_by_immediate()
10902 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_shift_by_immediate()
10915 Bool is2 = bitQ == 1; in dis_AdvSIMD_shift_by_immediate()
10931 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_shift_by_immediate()
10949 Bool is2 = bitQ == 1; in dis_AdvSIMD_shift_by_immediate()
10991 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_shift_by_immediate()
11011 Bool isQ = bitQ == 1; in dis_AdvSIMD_shift_by_immediate()
11080 Bool isQ = bitQ == 1; in dis_AdvSIMD_shift_by_immediate()
11106 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_shift_by_immediate()
11126 Bool isQ = bitQ == 1; in dis_AdvSIMD_shift_by_immediate()
11153 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_shift_by_immediate()
11179 UInt bitQ = INSN(30,30); in dis_AdvSIMD_three_different() local
11187 Bool is2 = bitQ == 1; in dis_AdvSIMD_three_different()
11205 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_different()
11230 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_different()
11269 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_different()
11296 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_different()
11336 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_different()
11377 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_different()
11399 arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_different()
11418 arrNarrow = bitQ == 0 ? "1d" : "2d"; in dis_AdvSIMD_three_different()
11447 UInt bitQ = INSN(30,30); in dis_AdvSIMD_three_same() local
11489 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11492 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11501 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11508 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11509 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11520 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11539 bitQ, binop(qop, mkexpr(argL), mkexpr(argR)))); in dis_AdvSIMD_three_same()
11541 bitQ, binop(nop, mkexpr(argL), mkexpr(argR)))); in dis_AdvSIMD_three_same()
11546 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11564 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11566 const HChar* ar = bitQ == 1 ? "16b" : "8b"; in dis_AdvSIMD_three_same()
11612 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11614 const HChar* arr = bitQ == 1 ? "16b" : "8b"; in dis_AdvSIMD_three_same()
11623 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11631 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11633 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11642 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11650 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11652 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11663 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11670 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11673 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11684 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11701 math_MAYBE_ZERO_HI64_fromE(bitQ, getQReg128(nn)), in dis_AdvSIMD_three_same()
11702 math_MAYBE_ZERO_HI64_fromE(bitQ, getQReg128(mm)))); in dis_AdvSIMD_three_same()
11710 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11721 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11728 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t)); in dis_AdvSIMD_three_same()
11731 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11750 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t2)); in dis_AdvSIMD_three_same()
11753 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11762 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11767 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t)); in dis_AdvSIMD_three_same()
11769 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11778 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11788 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11790 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11799 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11808 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11809 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11820 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11828 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11829 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11859 = bitQ == 0 ? unop(Iop_ZeroHI64ofV128, in dis_AdvSIMD_three_same()
11864 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11883 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11884 IROp opZHI = bitQ == 0 ? Iop_ZeroHI64ofV128 : Iop_INVALID; in dis_AdvSIMD_three_same()
11886 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11895 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_three_same()
11908 = bitQ == 0 ? unop(Iop_ZeroHI64ofV128, in dis_AdvSIMD_three_same()
11913 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_three_same()
11927 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
11933 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11934 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
11946 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
11958 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t2)); in dis_AdvSIMD_three_same()
11959 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
11970 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
11978 assign(t2, math_MAYBE_ZERO_HI64(bitQ, t1)); in dis_AdvSIMD_three_same()
11980 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
11989 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
11998 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t2)); in dis_AdvSIMD_three_same()
11999 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12011 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12016 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t1)); in dis_AdvSIMD_three_same()
12017 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12027 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12034 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t1)); in dis_AdvSIMD_three_same()
12035 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12044 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12048 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t1)); in dis_AdvSIMD_three_same()
12049 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12060 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12067 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t1)); in dis_AdvSIMD_three_same()
12068 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12082 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12093 srcM, srcN, isD, bitQ); in dis_AdvSIMD_three_same()
12096 bitQ, in dis_AdvSIMD_three_same()
12098 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12108 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12116 srcM, srcN, isD, bitQ); in dis_AdvSIMD_three_same()
12119 bitQ, in dis_AdvSIMD_three_same()
12123 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12132 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12140 assign(t2, math_MAYBE_ZERO_HI64(bitQ, t1)); in dis_AdvSIMD_three_same()
12142 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12153 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12158 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
12159 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12184 UInt bitQ = INSN(30,30); in dis_AdvSIMD_two_reg_misc() local
12201 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12202 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12215 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12216 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12226 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12227 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12254 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12255 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12256 const HChar* arrWide = nameArr_Q_SZ(bitQ, size+1); in dis_AdvSIMD_two_reg_misc()
12266 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12285 bitQ, binop(qop, mkexpr(argL), mkexpr(argR)))); in dis_AdvSIMD_two_reg_misc()
12287 bitQ, binop(nop, mkexpr(argL), mkexpr(argR)))); in dis_AdvSIMD_two_reg_misc()
12290 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12306 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12307 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12318 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12319 const HChar* arr = nameArr_Q_SZ(bitQ, 0); in dis_AdvSIMD_two_reg_misc()
12329 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12330 const HChar* arr = nameArr_Q_SZ(bitQ, 0); in dis_AdvSIMD_two_reg_misc()
12339 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12345 assign(qres, math_MAYBE_ZERO_HI64(bitQ, qresFW)); in dis_AdvSIMD_two_reg_misc()
12346 assign(nres, math_MAYBE_ZERO_HI64(bitQ, nresFW)); in dis_AdvSIMD_two_reg_misc()
12349 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12358 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12366 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12367 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12376 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12384 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12385 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12393 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12398 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12399 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12407 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12410 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12411 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12418 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12421 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12422 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12442 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12462 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12463 const HChar* arr = bitQ == 0 ? "2s" : (size == X11 ? "2d" : "4s"); in dis_AdvSIMD_two_reg_misc()
12472 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12478 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12479 const HChar* arr = bitQ == 0 ? "2s" : (size == X11 ? "2d" : "4s"); in dis_AdvSIMD_two_reg_misc()
12489 Bool is2 = bitQ == 1; in dis_AdvSIMD_two_reg_misc()
12495 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12509 Bool is2 = bitQ == 1; in dis_AdvSIMD_two_reg_misc()
12531 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12542 Bool is2 = bitQ == 1; in dis_AdvSIMD_two_reg_misc()
12551 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12570 putQRegLane(dd, nLanes * bitQ + i, in dis_AdvSIMD_two_reg_misc()
12573 if (bitQ == 0) { in dis_AdvSIMD_two_reg_misc()
12576 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, 1+size); in dis_AdvSIMD_two_reg_misc()
12578 DIP("fcvtn%s %s.%s, %s.%s\n", bitQ ? "2" : "", in dis_AdvSIMD_two_reg_misc()
12595 putQRegLane(dd, 2 * bitQ + i, in dis_AdvSIMD_two_reg_misc()
12598 if (bitQ == 0) { in dis_AdvSIMD_two_reg_misc()
12601 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, 1+size); in dis_AdvSIMD_two_reg_misc()
12603 DIP("fcvtxn%s %s.%s, %s.%s\n", bitQ ? "2" : "", in dis_AdvSIMD_two_reg_misc()
12616 assign(src[i], getQRegLane(nn, nLanes * bitQ + i, srcTy)); in dis_AdvSIMD_two_reg_misc()
12621 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, 1+size); in dis_AdvSIMD_two_reg_misc()
12623 DIP("fcvtl%s %s.%s, %s.%s\n", bitQ ? "2" : "", in dis_AdvSIMD_two_reg_misc()
12654 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12681 UInt n = bitQ==1 ? 4 : 2; in dis_AdvSIMD_two_reg_misc()
12686 if (bitQ == 0) in dis_AdvSIMD_two_reg_misc()
12689 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12714 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12738 UInt n = bitQ==1 ? 4 : 2; in dis_AdvSIMD_two_reg_misc()
12743 if (bitQ == 0) in dis_AdvSIMD_two_reg_misc()
12746 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12759 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12761 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_two_reg_misc()
12776 Bool isQ = bitQ == 1; in dis_AdvSIMD_two_reg_misc()
12812 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12815 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, resV)); in dis_AdvSIMD_two_reg_misc()
12816 const HChar* arr = bitQ == 0 ? "2s" : (size == X11 ? "2d" : "4s"); in dis_AdvSIMD_two_reg_misc()
12826 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12830 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, resV)); in dis_AdvSIMD_two_reg_misc()
12831 const HChar* arr = bitQ == 0 ? "2s" : (size == X11 ? "2d" : "4s"); in dis_AdvSIMD_two_reg_misc()
12856 UInt bitQ = INSN(30,30); in dis_AdvSIMD_vector_x_indexed_elem() local
12873 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_vector_x_indexed_elem()
12896 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t2)); in dis_AdvSIMD_vector_x_indexed_elem()
12897 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_vector_x_indexed_elem()
12907 if (bitQ == 0 && size == X11) return False; // implied 1d case in dis_AdvSIMD_vector_x_indexed_elem()
12925 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_vector_x_indexed_elem()
12926 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_vector_x_indexed_elem()
12971 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_vector_x_indexed_elem()
12972 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_vector_x_indexed_elem()
12998 Bool is2 = bitQ == 1; in dis_AdvSIMD_vector_x_indexed_elem()
13024 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_vector_x_indexed_elem()
13049 Bool is2 = bitQ == 1; in dis_AdvSIMD_vector_x_indexed_elem()
13082 const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_vector_x_indexed_elem()
13117 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_vector_x_indexed_elem()
13118 IROp opZHI = bitQ == 0 ? Iop_ZeroHI64ofV128 : Iop_INVALID; in dis_AdvSIMD_vector_x_indexed_elem()
13121 const HChar* arr = nameArr_Q_SZ(bitQ, size); in dis_AdvSIMD_vector_x_indexed_elem()