Lines Matching refs:bitU
8768 UInt bitU = INSN(29,29); in dis_AdvSIMD_across_lanes() local
8779 Bool isU = bitU == 1; in dis_AdvSIMD_across_lanes()
8810 /**/ if (opcode == BITS5(0,1,0,1,0)) { ix = bitU == 0 ? 1 : 2; } in dis_AdvSIMD_across_lanes()
8811 else if (opcode == BITS5(1,1,0,1,0)) { ix = bitU == 0 ? 3 : 4; } in dis_AdvSIMD_across_lanes()
8812 else if (opcode == BITS5(1,1,0,1,1) && bitU == 0) { ix = 5; } in dis_AdvSIMD_across_lanes()
9417 UInt bitU = INSN(29,29); in dis_AdvSIMD_scalar_pairwise() local
9423 if (bitU == 0 && sz == X11 && opcode == BITS5(1,1,0,1,1)) { in dis_AdvSIMD_scalar_pairwise()
9435 if (bitU == 1 && sz <= X01 && opcode == BITS5(0,1,1,0,1)) { in dis_AdvSIMD_scalar_pairwise()
9455 if (bitU == 1 in dis_AdvSIMD_scalar_pairwise()
9499 UInt bitU = INSN(29,29); in dis_AdvSIMD_scalar_shift_by_imm() local
9513 Bool isU = bitU == 1; in dis_AdvSIMD_scalar_shift_by_imm()
9546 Bool isU = bitU == 1; in dis_AdvSIMD_scalar_shift_by_imm()
9568 if (bitU == 1 && (immh & 8) == 8 && opcode == BITS5(0,1,0,0,0)) { in dis_AdvSIMD_scalar_shift_by_imm()
9588 if (bitU == 0 && (immh & 8) == 8 && opcode == BITS5(0,1,0,1,0)) { in dis_AdvSIMD_scalar_shift_by_imm()
9600 if (bitU == 1 && (immh & 8) == 8 && opcode == BITS5(0,1,0,1,0)) { in dis_AdvSIMD_scalar_shift_by_imm()
9621 || (bitU == 1 && opcode == BITS5(0,1,1,0,0))) { in dis_AdvSIMD_scalar_shift_by_imm()
9636 /**/ if (bitU == 0 && opcode == BITS5(0,1,1,1,0)) nm = "sqshl"; in dis_AdvSIMD_scalar_shift_by_imm()
9637 else if (bitU == 1 && opcode == BITS5(0,1,1,1,0)) nm = "uqshl"; in dis_AdvSIMD_scalar_shift_by_imm()
9638 else if (bitU == 1 && opcode == BITS5(0,1,1,0,0)) nm = "sqshlu"; in dis_AdvSIMD_scalar_shift_by_imm()
9656 || (bitU == 1 in dis_AdvSIMD_scalar_shift_by_imm()
9673 /**/ if (bitU == 0 && opcode == BITS5(1,0,0,1,0)) { in dis_AdvSIMD_scalar_shift_by_imm()
9676 else if (bitU == 1 && opcode == BITS5(1,0,0,1,0)) { in dis_AdvSIMD_scalar_shift_by_imm()
9679 else if (bitU == 0 && opcode == BITS5(1,0,0,1,1)) { in dis_AdvSIMD_scalar_shift_by_imm()
9682 else if (bitU == 1 && opcode == BITS5(1,0,0,1,1)) { in dis_AdvSIMD_scalar_shift_by_imm()
9685 else if (bitU == 1 && opcode == BITS5(1,0,0,0,0)) { in dis_AdvSIMD_scalar_shift_by_imm()
9688 else if (bitU == 1 && opcode == BITS5(1,0,0,0,1)) { in dis_AdvSIMD_scalar_shift_by_imm()
9724 Bool isU = bitU == 1; in dis_AdvSIMD_scalar_shift_by_imm()
9762 Bool isU = bitU == 1; in dis_AdvSIMD_scalar_shift_by_imm()
9810 UInt bitU = INSN(29,29); in dis_AdvSIMD_scalar_three_different() local
9818 if (bitU == 0 in dis_AdvSIMD_scalar_three_different()
9879 UInt bitU = INSN(29,29); in dis_AdvSIMD_scalar_three_same() local
9893 Bool isU = bitU == 1; in dis_AdvSIMD_scalar_three_same()
9925 Bool isGT = bitU == 0; in dis_AdvSIMD_scalar_three_same()
9942 Bool isGE = bitU == 0; in dis_AdvSIMD_scalar_three_same()
9962 Bool isU = bitU == 1; in dis_AdvSIMD_scalar_three_same()
9982 Bool isU = bitU == 1; in dis_AdvSIMD_scalar_three_same()
10015 Bool isSUB = bitU == 1; in dis_AdvSIMD_scalar_three_same()
10031 Bool isEQ = bitU == 1; in dis_AdvSIMD_scalar_three_same()
10051 Bool isR = bitU == 1; in dis_AdvSIMD_scalar_three_same()
10069 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,0,1,0)) { in dis_AdvSIMD_scalar_three_same()
10084 if (bitU == 0 && size <= X01 && opcode == BITS5(1,1,0,1,1)) { in dis_AdvSIMD_scalar_three_same()
10104 Bool isGE = bitU == 1; in dis_AdvSIMD_scalar_three_same()
10117 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,0,0)) { in dis_AdvSIMD_scalar_three_same()
10131 if (bitU == 1 && opcode == BITS5(1,1,1,0,1)) { in dis_AdvSIMD_scalar_three_same()
10150 if (bitU == 0 && opcode == BITS5(1,1,1,1,1)) { in dis_AdvSIMD_scalar_three_same()
10186 UInt bitU = INSN(29,29); in dis_AdvSIMD_scalar_two_reg_misc() local
10199 Bool isUSQADD = bitU == 1; in dis_AdvSIMD_scalar_two_reg_misc()
10221 Bool isNEG = bitU == 1; in dis_AdvSIMD_scalar_two_reg_misc()
10237 Bool isGT = bitU == 0; in dis_AdvSIMD_scalar_two_reg_misc()
10251 Bool isEQ = bitU == 0; in dis_AdvSIMD_scalar_two_reg_misc()
10263 if (bitU == 0 && size == X11 && opcode == BITS5(0,1,0,1,0)) { in dis_AdvSIMD_scalar_two_reg_misc()
10272 if (bitU == 0 && size == X11 && opcode == BITS5(0,1,0,1,1)) { in dis_AdvSIMD_scalar_two_reg_misc()
10280 if (bitU == 1 && size == X11 && opcode == BITS5(0,1,0,1,1)) { in dis_AdvSIMD_scalar_two_reg_misc()
10291 case BITS5(0,1,1,0,0): ix = (bitU == 1) ? 4 : 1; break; in dis_AdvSIMD_scalar_two_reg_misc()
10292 case BITS5(0,1,1,0,1): ix = (bitU == 1) ? 5 : 2; break; in dis_AdvSIMD_scalar_two_reg_misc()
10293 case BITS5(0,1,1,1,0): if (bitU == 0) ix = 3; break; in dis_AdvSIMD_scalar_two_reg_misc()
10331 || (bitU == 1 && opcode == BITS5(1,0,0,1,0))) { in dis_AdvSIMD_scalar_two_reg_misc()
10340 /**/ if (bitU == 0 && opcode == BITS5(1,0,1,0,0)) { in dis_AdvSIMD_scalar_two_reg_misc()
10343 else if (bitU == 1 && opcode == BITS5(1,0,1,0,0)) { in dis_AdvSIMD_scalar_two_reg_misc()
10346 else if (bitU == 1 && opcode == BITS5(1,0,0,1,0)) { in dis_AdvSIMD_scalar_two_reg_misc()
10367 if (opcode == BITS5(1,0,1,1,0) && bitU == 1 && size == X01) { in dis_AdvSIMD_scalar_two_reg_misc()
10412 if (bitU == 1) { in dis_AdvSIMD_scalar_two_reg_misc()
10427 DIP("fcvt%c%c %c%u, %c%u\n", ch, bitU == 1 ? 'u' : 's', in dis_AdvSIMD_scalar_two_reg_misc()
10435 Bool isU = bitU == 1; in dis_AdvSIMD_scalar_two_reg_misc()
10454 Bool isSQRT = bitU == 1; in dis_AdvSIMD_scalar_two_reg_misc()
10467 if (bitU == 0 && size >= X10 && opcode == BITS5(1,1,1,1,1)) { in dis_AdvSIMD_scalar_two_reg_misc()
10501 UInt bitU = INSN(29,29); in dis_AdvSIMD_scalar_x_indexed_element() local
10513 if (bitU == 0 && size >= X10 in dis_AdvSIMD_scalar_x_indexed_element()
10552 Bool isMULX = bitU == 1; in dis_AdvSIMD_scalar_x_indexed_element()
10577 if (bitU == 0 in dis_AdvSIMD_scalar_x_indexed_element()
10684 UInt bitU = INSN(29,29); in dis_AdvSIMD_shift_by_immediate() local
10706 Bool isU = bitU == 1; in dis_AdvSIMD_shift_by_immediate()
10755 Bool isU = bitU == 1; in dis_AdvSIMD_shift_by_immediate()
10783 if (bitU == 1 && opcode == BITS5(0,1,0,0,0)) { in dis_AdvSIMD_shift_by_immediate()
10835 Bool isSLI = bitU == 1; in dis_AdvSIMD_shift_by_immediate()
10873 || (bitU == 1 && opcode == BITS5(0,1,1,0,0))) { in dis_AdvSIMD_shift_by_immediate()
10889 /**/ if (bitU == 0 && opcode == BITS5(0,1,1,1,0)) nm = "sqshl"; in dis_AdvSIMD_shift_by_immediate()
10890 else if (bitU == 1 && opcode == BITS5(0,1,1,1,0)) nm = "uqshl"; in dis_AdvSIMD_shift_by_immediate()
10891 else if (bitU == 1 && opcode == BITS5(0,1,1,0,0)) nm = "sqshlu"; in dis_AdvSIMD_shift_by_immediate()
10908 if (bitU == 0 in dis_AdvSIMD_shift_by_immediate()
10939 || (bitU == 1 in dis_AdvSIMD_shift_by_immediate()
10956 /**/ if (bitU == 0 && opcode == BITS5(1,0,0,1,0)) { in dis_AdvSIMD_shift_by_immediate()
10959 else if (bitU == 1 && opcode == BITS5(1,0,0,1,0)) { in dis_AdvSIMD_shift_by_immediate()
10962 else if (bitU == 0 && opcode == BITS5(1,0,0,1,1)) { in dis_AdvSIMD_shift_by_immediate()
10965 else if (bitU == 1 && opcode == BITS5(1,0,0,1,1)) { in dis_AdvSIMD_shift_by_immediate()
10968 else if (bitU == 1 && opcode == BITS5(1,0,0,0,0)) { in dis_AdvSIMD_shift_by_immediate()
10971 else if (bitU == 1 && opcode == BITS5(1,0,0,0,1)) { in dis_AdvSIMD_shift_by_immediate()
11012 Bool isU = bitU == 1; in dis_AdvSIMD_shift_by_immediate()
11079 Bool isU = bitU == 1; in dis_AdvSIMD_shift_by_immediate()
11125 Bool isU = bitU == 1; in dis_AdvSIMD_shift_by_immediate()
11180 UInt bitU = INSN(29,29); in dis_AdvSIMD_three_different() local
11197 Bool isU = bitU == 1; in dis_AdvSIMD_three_different()
11223 Bool isU = bitU == 1; in dis_AdvSIMD_three_different()
11250 Bool isR = bitU == 1; in dis_AdvSIMD_three_different()
11287 Bool isU = bitU == 1; in dis_AdvSIMD_three_different()
11325 Bool isU = bitU == 1; in dis_AdvSIMD_three_different()
11345 if (bitU == 0 in dis_AdvSIMD_three_different()
11387 if (bitU == 0 && opcode == BITS4(1,1,1,0)) { in dis_AdvSIMD_three_different()
11448 UInt bitU = INSN(29,29); in dis_AdvSIMD_three_same() local
11463 Bool isU = bitU == 1; in dis_AdvSIMD_three_same()
11502 Bool isU = bitU == 1; in dis_AdvSIMD_three_same()
11522 Bool isU = bitU == 1; in dis_AdvSIMD_three_same()
11552 if (bitU == 0 && opcode == BITS5(0,0,0,1,1)) { in dis_AdvSIMD_three_same()
11572 if (bitU == 1 && opcode == BITS5(0,0,0,1,1)) { in dis_AdvSIMD_three_same()
11624 Bool isGT = bitU == 0; in dis_AdvSIMD_three_same()
11643 Bool isGE = bitU == 0; in dis_AdvSIMD_three_same()
11664 Bool isU = bitU == 1; in dis_AdvSIMD_three_same()
11685 Bool isU = bitU == 1; in dis_AdvSIMD_three_same()
11722 Bool isU = bitU == 1; in dis_AdvSIMD_three_same()
11743 Bool isU = bitU == 1; in dis_AdvSIMD_three_same()
11763 Bool isSUB = bitU == 1; in dis_AdvSIMD_three_same()
11779 Bool isEQ = bitU == 1; in dis_AdvSIMD_three_same()
11800 Bool isMLS = bitU == 1; in dis_AdvSIMD_three_same()
11821 Bool isPMUL = bitU == 1; in dis_AdvSIMD_three_same()
11843 Bool isU = bitU == 1; in dis_AdvSIMD_three_same()
11876 Bool isR = bitU == 1; in dis_AdvSIMD_three_same()
11893 if (bitU == 0 && opcode == BITS5(1,0,1,1,1)) { in dis_AdvSIMD_three_same()
11919 if (bitU == 0 in dis_AdvSIMD_three_same()
11941 if (bitU == 0 && opcode == BITS5(1,1,0,0,1)) { in dis_AdvSIMD_three_same()
11965 if (bitU == 0 && opcode == BITS5(1,1,0,1,0)) { in dis_AdvSIMD_three_same()
11986 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,0,1,0)) { in dis_AdvSIMD_three_same()
12010 Bool isMULX = bitU == 0; in dis_AdvSIMD_three_same()
12028 Bool isGE = bitU == 1; in dis_AdvSIMD_three_same()
12041 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,0,0)) { in dis_AdvSIMD_three_same()
12055 if (bitU == 1 && opcode == BITS5(1,1,1,0,1)) { in dis_AdvSIMD_three_same()
12074 if (bitU == 1 in dis_AdvSIMD_three_same()
12105 if (bitU == 1 && size <= X01 && opcode == BITS5(1,1,0,1,0)) { in dis_AdvSIMD_three_same()
12129 if (bitU == 1 && size <= X01 && opcode == BITS5(1,1,1,1,1)) { in dis_AdvSIMD_three_same()
12148 if (bitU == 0 && opcode == BITS5(1,1,1,1,1)) { in dis_AdvSIMD_three_same()
12185 UInt bitU = INSN(29,29); in dis_AdvSIMD_two_reg_misc() local
12192 if (bitU == 0 && size <= X10 && opcode == BITS5(0,0,0,0,0)) { in dis_AdvSIMD_two_reg_misc()
12208 if (bitU == 1 && size <= X01 && opcode == BITS5(0,0,0,0,0)) { in dis_AdvSIMD_two_reg_misc()
12222 if (bitU == 0 && size == X00 && opcode == BITS5(0,0,0,0,1)) { in dis_AdvSIMD_two_reg_misc()
12240 Bool isU = bitU == 1; in dis_AdvSIMD_two_reg_misc()
12267 Bool isUSQADD = bitU == 1; in dis_AdvSIMD_two_reg_misc()
12302 Bool isCLZ = bitU == 1; in dis_AdvSIMD_two_reg_misc()
12317 assign(res, unop(bitU == 0 ? Iop_Cnt8x16 : Iop_NotV128, getQReg128(nn))); in dis_AdvSIMD_two_reg_misc()
12320 DIP("%s %s.%s, %s.%s\n", bitU == 0 ? "cnt" : "not", in dis_AdvSIMD_two_reg_misc()
12325 if (bitU == 1 && size == X01 && opcode == BITS5(0,0,1,0,1)) { in dis_AdvSIMD_two_reg_misc()
12340 Bool isNEG = bitU == 1; in dis_AdvSIMD_two_reg_misc()
12359 Bool isGT = bitU == 0; in dis_AdvSIMD_two_reg_misc()
12377 Bool isEQ = bitU == 0; in dis_AdvSIMD_two_reg_misc()
12391 if (bitU == 0 && opcode == BITS5(0,1,0,1,0)) { in dis_AdvSIMD_two_reg_misc()
12405 if (bitU == 0 && opcode == BITS5(0,1,0,1,1)) { in dis_AdvSIMD_two_reg_misc()
12416 if (bitU == 1 && opcode == BITS5(0,1,0,1,1)) { in dis_AdvSIMD_two_reg_misc()
12430 case BITS5(0,1,1,0,0): ix = (bitU == 1) ? 4 : 1; break; in dis_AdvSIMD_two_reg_misc()
12431 case BITS5(0,1,1,0,1): ix = (bitU == 1) ? 5 : 2; break; in dis_AdvSIMD_two_reg_misc()
12432 case BITS5(0,1,1,1,0): if (bitU == 0) ix = 3; break; in dis_AdvSIMD_two_reg_misc()
12473 Bool isFNEG = bitU == 1; in dis_AdvSIMD_two_reg_misc()
12485 if (bitU == 0 && opcode == BITS5(1,0,0,1,0)) { in dis_AdvSIMD_two_reg_misc()
12503 || (bitU == 1 && opcode == BITS5(1,0,0,1,0))) { in dis_AdvSIMD_two_reg_misc()
12513 /**/ if (bitU == 0 && opcode == BITS5(1,0,1,0,0)) { in dis_AdvSIMD_two_reg_misc()
12516 else if (bitU == 1 && opcode == BITS5(1,0,1,0,0)) { in dis_AdvSIMD_two_reg_misc()
12519 else if (bitU == 1 && opcode == BITS5(1,0,0,1,0)) { in dis_AdvSIMD_two_reg_misc()
12538 if (bitU == 1 && opcode == BITS5(1,0,0,1,1)) { in dis_AdvSIMD_two_reg_misc()
12558 if (bitU == 0 && size <= X01 && opcode == BITS5(1,0,1,1,0)) { in dis_AdvSIMD_two_reg_misc()
12583 if (bitU == 1 && size == X01 && opcode == BITS5(1,0,1,1,0)) { in dis_AdvSIMD_two_reg_misc()
12608 if (bitU == 0 && size <= X01 && opcode == BITS5(1,0,1,1,1)) { in dis_AdvSIMD_two_reg_misc()
12630 ix = 1 + ((((bitU & 1) << 2) | ((size & 2) << 0)) | ((opcode & 1) << 0)); in dis_AdvSIMD_two_reg_misc()
12727 if (bitU == 1) { in dis_AdvSIMD_two_reg_misc()
12747 DIP("fcvt%c%c %s.%s, %s.%s\n", ch, bitU == 1 ? 'u' : 's', in dis_AdvSIMD_two_reg_misc()
12755 Bool isREC = bitU == 0; in dis_AdvSIMD_two_reg_misc()
12777 Bool isU = bitU == 1; in dis_AdvSIMD_two_reg_misc()
12808 Bool isSQRT = bitU == 1; in dis_AdvSIMD_two_reg_misc()
12822 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,1,1)) { in dis_AdvSIMD_two_reg_misc()
12857 UInt bitU = INSN(29,29); in dis_AdvSIMD_vector_x_indexed_elem() local
12869 if (bitU == 0 && size >= X10 in dis_AdvSIMD_vector_x_indexed_elem()
12909 Bool isMULX = bitU == 1; in dis_AdvSIMD_vector_x_indexed_elem()
12933 if ((bitU == 1 && (opcode == BITS4(0,0,0,0) || opcode == BITS4(0,1,0,0))) in dis_AdvSIMD_vector_x_indexed_elem()
12934 || (bitU == 0 && opcode == BITS4(1,0,0,0))) { in dis_AdvSIMD_vector_x_indexed_elem()
12997 Bool isU = bitU == 1; in dis_AdvSIMD_vector_x_indexed_elem()
13034 if (bitU == 0 in dis_AdvSIMD_vector_x_indexed_elem()