Lines Matching refs:isD
8469 IRTemp vecM, IRTemp vecN, Bool isD, UInt bitQ in math_REARRANGE_FOR_FLOATING_PAIRWISE() argument
8476 if (isD) { in math_REARRANGE_FOR_FLOATING_PAIRWISE()
8482 else if (!isD && bitQ == 1) { in math_REARRANGE_FOR_FLOATING_PAIRWISE()
8488 vassert(!isD && bitQ == 0); in math_REARRANGE_FOR_FLOATING_PAIRWISE()
9438 Bool isD = sz == X01; in dis_AdvSIMD_scalar_pairwise() local
9439 IROp opZHI = mkVecZEROHIxxOFV128(isD ? 3 : 2); in dis_AdvSIMD_scalar_pairwise()
9440 IROp opADD = mkVecADDF(isD ? 3 : 2); in dis_AdvSIMD_scalar_pairwise()
9447 mkU8(isD ? 8 : 4)))); in dis_AdvSIMD_scalar_pairwise()
9451 DIP(isD ? "faddp d%u, v%u.2d\n" : "faddp s%u, v%u.2s\n", dd, nn); in dis_AdvSIMD_scalar_pairwise()
9462 Bool isD = (sz & 1) == 1; in dis_AdvSIMD_scalar_pairwise() local
9465 IROp opZHI = mkVecZEROHIxxOFV128(isD ? 3 : 2); in dis_AdvSIMD_scalar_pairwise()
9466 IROp opMXX = (isMIN ? mkVecMINF : mkVecMAXF)(isD ? 3 : 2); in dis_AdvSIMD_scalar_pairwise()
9473 mkU8(isD ? 8 : 4)))); in dis_AdvSIMD_scalar_pairwise()
9476 HChar c = isD ? 'd' : 's'; in dis_AdvSIMD_scalar_pairwise()
9723 Bool isD = size == X11; in dis_AdvSIMD_scalar_shift_by_imm() local
9725 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32)); in dis_AdvSIMD_scalar_shift_by_imm()
9727 IRExpr* scaleE = isD ? IRExpr_Const(IRConst_F64(scale)) in dis_AdvSIMD_scalar_shift_by_imm()
9729 IROp opMUL = isD ? Iop_MulF64 : Iop_MulF32; in dis_AdvSIMD_scalar_shift_by_imm()
9730 IROp opCVT = isU ? (isD ? Iop_I64UtoF64 : Iop_I32UtoF32) in dis_AdvSIMD_scalar_shift_by_imm()
9731 : (isD ? Iop_I64StoF64 : Iop_I32StoF32); in dis_AdvSIMD_scalar_shift_by_imm()
9732 IRType tyF = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_shift_by_imm()
9733 IRType tyI = isD ? Ity_I64 : Ity_I32; in dis_AdvSIMD_scalar_shift_by_imm()
9741 if (!isD) { in dis_AdvSIMD_scalar_shift_by_imm()
9745 const HChar ch = isD ? 'd' : 's'; in dis_AdvSIMD_scalar_shift_by_imm()
9761 Bool isD = size == X11; in dis_AdvSIMD_scalar_shift_by_imm() local
9763 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32)); in dis_AdvSIMD_scalar_shift_by_imm()
9765 IRExpr* scaleE = isD ? IRExpr_Const(IRConst_F64(scale)) in dis_AdvSIMD_scalar_shift_by_imm()
9767 IROp opMUL = isD ? Iop_MulF64 : Iop_MulF32; in dis_AdvSIMD_scalar_shift_by_imm()
9768 IROp opCVT = isU ? (isD ? Iop_F64toI64U : Iop_F32toI32U) in dis_AdvSIMD_scalar_shift_by_imm()
9769 : (isD ? Iop_F64toI64S : Iop_F32toI32S); in dis_AdvSIMD_scalar_shift_by_imm()
9770 IRType tyF = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_shift_by_imm()
9771 IRType tyI = isD ? Ity_I64 : Ity_I32; in dis_AdvSIMD_scalar_shift_by_imm()
9780 if (!isD) { in dis_AdvSIMD_scalar_shift_by_imm()
9784 const HChar ch = isD ? 'd' : 's'; in dis_AdvSIMD_scalar_shift_by_imm()
10102 Bool isD = size == X01; in dis_AdvSIMD_scalar_three_same() local
10103 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_three_same()
10105 IROp opCMP = isGE ? (isD ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4) in dis_AdvSIMD_scalar_three_same()
10106 : (isD ? Iop_CmpEQ64Fx2 : Iop_CmpEQ32Fx4); in dis_AdvSIMD_scalar_three_same()
10110 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_three_same()
10119 Bool isD = size == X11; in dis_AdvSIMD_scalar_three_same() local
10120 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_three_same()
10121 IROp opCMP = isD ? Iop_CmpLT64Fx2 : Iop_CmpLT32Fx4; in dis_AdvSIMD_scalar_three_same()
10124 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_three_same()
10134 Bool isD = (size & 1) == 1; in dis_AdvSIMD_scalar_three_same() local
10135 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_three_same()
10137 IROp opCMP = isGT ? (isD ? Iop_CmpLT64Fx2 : Iop_CmpLT32Fx4) in dis_AdvSIMD_scalar_three_same()
10138 : (isD ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4); in dis_AdvSIMD_scalar_three_same()
10139 IROp opABS = isD ? Iop_Abs64Fx2 : Iop_Abs32Fx4; in dis_AdvSIMD_scalar_three_same()
10143 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_three_same()
10154 Bool isD = (size & 1) == 1; in dis_AdvSIMD_scalar_three_same() local
10155 IROp op = isSQRT ? (isD ? Iop_RSqrtStep64Fx2 : Iop_RSqrtStep32Fx4) in dis_AdvSIMD_scalar_three_same()
10156 : (isD ? Iop_RecipStep64Fx2 : Iop_RecipStep32Fx4); in dis_AdvSIMD_scalar_three_same()
10159 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_three_same()
10161 HChar c = isD ? 'd' : 's'; in dis_AdvSIMD_scalar_three_same()
10303 Bool isD = size == X11; in dis_AdvSIMD_scalar_two_reg_misc() local
10304 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_two_reg_misc()
10305 IROp opCmpEQ = isD ? Iop_CmpEQ64Fx2 : Iop_CmpEQ32Fx4; in dis_AdvSIMD_scalar_two_reg_misc()
10306 IROp opCmpLE = isD ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4; in dis_AdvSIMD_scalar_two_reg_misc()
10307 IROp opCmpLT = isD ? Iop_CmpLT64Fx2 : Iop_CmpLT32Fx4; in dis_AdvSIMD_scalar_two_reg_misc()
10323 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_two_reg_misc()
10398 Bool isD = (size & 1) == 1; in dis_AdvSIMD_scalar_two_reg_misc() local
10399 IRType tyF = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_two_reg_misc()
10400 IRType tyI = isD ? Ity_I64 : Ity_I32; in dis_AdvSIMD_scalar_two_reg_misc()
10413 cvt = isD ? Iop_F64toI64U : Iop_F32toI32U; in dis_AdvSIMD_scalar_two_reg_misc()
10415 cvt = isD ? Iop_F64toI64S : Iop_F32toI32S; in dis_AdvSIMD_scalar_two_reg_misc()
10422 if (!isD) { in dis_AdvSIMD_scalar_two_reg_misc()
10426 HChar sOrD = isD ? 'd' : 's'; in dis_AdvSIMD_scalar_two_reg_misc()
10436 Bool isD = (size & 1) == 1; in dis_AdvSIMD_scalar_two_reg_misc() local
10437 IRType tyI = isD ? Ity_I64 : Ity_I32; in dis_AdvSIMD_scalar_two_reg_misc()
10438 IROp iop = isU ? (isD ? Iop_I64UtoF64 : Iop_I32UtoF32) in dis_AdvSIMD_scalar_two_reg_misc()
10439 : (isD ? Iop_I64StoF64 : Iop_I32StoF32); in dis_AdvSIMD_scalar_two_reg_misc()
10442 if (!isD) { in dis_AdvSIMD_scalar_two_reg_misc()
10446 HChar c = isD ? 'd' : 's'; in dis_AdvSIMD_scalar_two_reg_misc()
10455 Bool isD = (size & 1) == 1; in dis_AdvSIMD_scalar_two_reg_misc() local
10456 IROp op = isSQRT ? (isD ? Iop_RSqrtEst64Fx2 : Iop_RSqrtEst32Fx4) in dis_AdvSIMD_scalar_two_reg_misc()
10457 : (isD ? Iop_RecipEst64Fx2 : Iop_RecipEst32Fx4); in dis_AdvSIMD_scalar_two_reg_misc()
10460 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_two_reg_misc()
10462 HChar c = isD ? 'd' : 's'; in dis_AdvSIMD_scalar_two_reg_misc()
10469 Bool isD = (size & 1) == 1; in dis_AdvSIMD_scalar_two_reg_misc() local
10470 IRType ty = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_two_reg_misc()
10471 IROp op = isD ? Iop_RecpExpF64 : Iop_RecpExpF32; in dis_AdvSIMD_scalar_two_reg_misc()
10477 HChar c = isD ? 'd' : 's'; in dis_AdvSIMD_scalar_two_reg_misc()
10517 Bool isD = (size & 1) == 1; in dis_AdvSIMD_scalar_x_indexed_element() local
10520 if (!isD) index = (bitH << 1) | bitL; in dis_AdvSIMD_scalar_x_indexed_element()
10521 else if (isD && bitL == 0) index = bitH; in dis_AdvSIMD_scalar_x_indexed_element()
10523 vassert(index < (isD ? 2 : 4)); in dis_AdvSIMD_scalar_x_indexed_element()
10524 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_x_indexed_element()
10529 IROp opADD = isD ? Iop_Add64Fx2 : Iop_Add32Fx4; in dis_AdvSIMD_scalar_x_indexed_element()
10530 IROp opSUB = isD ? Iop_Sub64Fx2 : Iop_Sub32Fx4; in dis_AdvSIMD_scalar_x_indexed_element()
10531 IROp opMUL = isD ? Iop_Mul64Fx2 : Iop_Mul32Fx4; in dis_AdvSIMD_scalar_x_indexed_element()
10540 mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? 3 : 2, in dis_AdvSIMD_scalar_x_indexed_element()
10542 const HChar c = isD ? 'd' : 's'; in dis_AdvSIMD_scalar_x_indexed_element()
10551 Bool isD = (size & 1) == 1; in dis_AdvSIMD_scalar_x_indexed_element() local
10554 if (!isD) index = (bitH << 1) | bitL; in dis_AdvSIMD_scalar_x_indexed_element()
10555 else if (isD && bitL == 0) index = bitH; in dis_AdvSIMD_scalar_x_indexed_element()
10557 vassert(index < (isD ? 2 : 4)); in dis_AdvSIMD_scalar_x_indexed_element()
10558 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_x_indexed_element()
10563 IROp opMUL = isD ? Iop_Mul64Fx2 : Iop_Mul32Fx4; in dis_AdvSIMD_scalar_x_indexed_element()
10569 mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? 3 : 2, in dis_AdvSIMD_scalar_x_indexed_element()
10571 const HChar c = isD ? 'd' : 's'; in dis_AdvSIMD_scalar_x_indexed_element()
11078 Bool isD = size == X11; in dis_AdvSIMD_shift_by_immediate() local
11081 if (isD && !isQ) return False; /* reject .1d case */ in dis_AdvSIMD_shift_by_immediate()
11082 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32)); in dis_AdvSIMD_shift_by_immediate()
11084 IRExpr* scaleE = isD ? IRExpr_Const(IRConst_F64(scale)) in dis_AdvSIMD_shift_by_immediate()
11086 IROp opMUL = isD ? Iop_MulF64 : Iop_MulF32; in dis_AdvSIMD_shift_by_immediate()
11087 IROp opCVT = isU ? (isD ? Iop_I64UtoF64 : Iop_I32UtoF32) in dis_AdvSIMD_shift_by_immediate()
11088 : (isD ? Iop_I64StoF64 : Iop_I32StoF32); in dis_AdvSIMD_shift_by_immediate()
11089 IRType tyF = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_shift_by_immediate()
11090 IRType tyI = isD ? Ity_I64 : Ity_I32; in dis_AdvSIMD_shift_by_immediate()
11091 UInt nLanes = (isQ ? 2 : 1) * (isD ? 1 : 2); in dis_AdvSIMD_shift_by_immediate()
11124 Bool isD = size == X11; in dis_AdvSIMD_shift_by_immediate() local
11127 if (isD && !isQ) return False; /* reject .1d case */ in dis_AdvSIMD_shift_by_immediate()
11128 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32)); in dis_AdvSIMD_shift_by_immediate()
11130 IRExpr* scaleE = isD ? IRExpr_Const(IRConst_F64(scale)) in dis_AdvSIMD_shift_by_immediate()
11132 IROp opMUL = isD ? Iop_MulF64 : Iop_MulF32; in dis_AdvSIMD_shift_by_immediate()
11133 IROp opCVT = isU ? (isD ? Iop_F64toI64U : Iop_F32toI32U) in dis_AdvSIMD_shift_by_immediate()
11134 : (isD ? Iop_F64toI64S : Iop_F32toI32S); in dis_AdvSIMD_shift_by_immediate()
11135 IRType tyF = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_shift_by_immediate()
11136 IRType tyI = isD ? Ity_I64 : Ity_I32; in dis_AdvSIMD_shift_by_immediate()
11137 UInt nLanes = (isQ ? 2 : 1) * (isD ? 1 : 2); in dis_AdvSIMD_shift_by_immediate()
11926 Bool isD = (size & 1) == 1; in dis_AdvSIMD_three_same() local
11927 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
11930 IROp opMXX = (isMIN ? mkVecMINF : mkVecMAXF)(isD ? X11 : X10); in dis_AdvSIMD_three_same()
11934 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
11944 Bool isD = (size & 1) == 1; in dis_AdvSIMD_three_same() local
11946 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
11947 IROp opADD = isD ? Iop_Add64Fx2 : Iop_Add32Fx4; in dis_AdvSIMD_three_same()
11948 IROp opSUB = isD ? Iop_Sub64Fx2 : Iop_Sub32Fx4; in dis_AdvSIMD_three_same()
11949 IROp opMUL = isD ? Iop_Mul64Fx2 : Iop_Mul32Fx4; in dis_AdvSIMD_three_same()
11959 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
11968 Bool isD = (size & 1) == 1; in dis_AdvSIMD_three_same() local
11970 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
11980 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
11988 Bool isD = (size & 1) == 1; in dis_AdvSIMD_three_same() local
11989 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
11990 IROp opSUB = isD ? Iop_Sub64Fx2 : Iop_Sub32Fx4; in dis_AdvSIMD_three_same()
11991 IROp opABS = isD ? Iop_Abs64Fx2 : Iop_Abs32Fx4; in dis_AdvSIMD_three_same()
11999 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12009 Bool isD = (size & 1) == 1; in dis_AdvSIMD_three_same() local
12011 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12014 assign(t1, triop(isD ? Iop_Mul64Fx2 : Iop_Mul32Fx4, in dis_AdvSIMD_three_same()
12017 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12026 Bool isD = (size & 1) == 1; in dis_AdvSIMD_three_same() local
12027 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12029 IROp opCMP = isGE ? (isD ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4) in dis_AdvSIMD_three_same()
12030 : (isD ? Iop_CmpEQ64Fx2 : Iop_CmpEQ32Fx4); in dis_AdvSIMD_three_same()
12035 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12043 Bool isD = (size & 1) == 1; in dis_AdvSIMD_three_same() local
12044 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12045 IROp opCMP = isD ? Iop_CmpLT64Fx2 : Iop_CmpLT32Fx4; in dis_AdvSIMD_three_same()
12049 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12058 Bool isD = (size & 1) == 1; in dis_AdvSIMD_three_same() local
12060 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12061 IROp opCMP = isGT ? (isD ? Iop_CmpLT64Fx2 : Iop_CmpLT32Fx4) in dis_AdvSIMD_three_same()
12062 : (isD ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4); in dis_AdvSIMD_three_same()
12063 IROp opABS = isD ? Iop_Abs64Fx2 : Iop_Abs32Fx4; in dis_AdvSIMD_three_same()
12068 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12081 Bool isD = (size & 1) == 1; in dis_AdvSIMD_three_same() local
12082 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12085 IROp opMXX = (isMIN ? mkVecMINF : mkVecMAXF)(isD ? 3 : 2); in dis_AdvSIMD_three_same()
12093 srcM, srcN, isD, bitQ); in dis_AdvSIMD_three_same()
12098 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12107 Bool isD = size == X01; in dis_AdvSIMD_three_same() local
12108 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12116 srcM, srcN, isD, bitQ); in dis_AdvSIMD_three_same()
12120 triop(mkVecADDF(isD ? 3 : 2), in dis_AdvSIMD_three_same()
12123 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12131 Bool isD = (size & 1) == 1; in dis_AdvSIMD_three_same() local
12132 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12142 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12152 Bool isD = (size & 1) == 1; in dis_AdvSIMD_three_same() local
12153 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_three_same()
12154 IROp op = isSQRT ? (isD ? Iop_RSqrtStep64Fx2 : Iop_RSqrtStep32Fx4) in dis_AdvSIMD_three_same()
12155 : (isD ? Iop_RecipStep64Fx2 : Iop_RecipStep32Fx4); in dis_AdvSIMD_three_same()
12159 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_three_same()
12443 Bool isD = size == X11; in dis_AdvSIMD_two_reg_misc() local
12444 IROp opCmpEQ = isD ? Iop_CmpEQ64Fx2 : Iop_CmpEQ32Fx4; in dis_AdvSIMD_two_reg_misc()
12445 IROp opCmpLE = isD ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4; in dis_AdvSIMD_two_reg_misc()
12446 IROp opCmpLT = isD ? Iop_CmpLT64Fx2 : Iop_CmpLT32Fx4; in dis_AdvSIMD_two_reg_misc()
12653 Bool isD = (size & 1) == 1; in dis_AdvSIMD_two_reg_misc() local
12654 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12674 IROp opRND = isD ? Iop_RoundF64toInt : Iop_RoundF32toInt; in dis_AdvSIMD_two_reg_misc()
12675 if (isD) { in dis_AdvSIMD_two_reg_misc()
12713 Bool isD = (size & 1) == 1; in dis_AdvSIMD_two_reg_misc() local
12714 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12728 cvt = isD ? Iop_F64toI64U : Iop_F32toI32U; in dis_AdvSIMD_two_reg_misc()
12730 cvt = isD ? Iop_F64toI64S : Iop_F32toI32S; in dis_AdvSIMD_two_reg_misc()
12732 if (isD) { in dis_AdvSIMD_two_reg_misc()
12809 Bool isD = (size & 1) == 1; in dis_AdvSIMD_two_reg_misc() local
12810 IROp op = isSQRT ? (isD ? Iop_RSqrtEst64Fx2 : Iop_RSqrtEst32Fx4) in dis_AdvSIMD_two_reg_misc()
12811 : (isD ? Iop_RecipEst64Fx2 : Iop_RecipEst32Fx4); in dis_AdvSIMD_two_reg_misc()
12812 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12824 Bool isD = (size & 1) == 1; in dis_AdvSIMD_two_reg_misc() local
12825 IROp op = isD ? Iop_Sqrt64Fx2 : Iop_Sqrt32Fx4; in dis_AdvSIMD_two_reg_misc()
12826 if (bitQ == 0 && isD) return False; // implied 1d case in dis_AdvSIMD_two_reg_misc()
12874 Bool isD = (size & 1) == 1; in dis_AdvSIMD_vector_x_indexed_elem() local
12877 if (!isD) index = (bitH << 1) | bitL; in dis_AdvSIMD_vector_x_indexed_elem()
12878 else if (isD && bitL == 0) index = bitH; in dis_AdvSIMD_vector_x_indexed_elem()
12880 vassert(index < (isD ? 2 : 4)); in dis_AdvSIMD_vector_x_indexed_elem()
12881 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_vector_x_indexed_elem()
12886 IROp opADD = isD ? Iop_Add64Fx2 : Iop_Add32Fx4; in dis_AdvSIMD_vector_x_indexed_elem()
12887 IROp opSUB = isD ? Iop_Sub64Fx2 : Iop_Sub32Fx4; in dis_AdvSIMD_vector_x_indexed_elem()
12888 IROp opMUL = isD ? Iop_Mul64Fx2 : Iop_Mul32Fx4; in dis_AdvSIMD_vector_x_indexed_elem()
12897 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_vector_x_indexed_elem()
12900 isD ? 'd' : 's', index); in dis_AdvSIMD_vector_x_indexed_elem()
12908 Bool isD = (size & 1) == 1; in dis_AdvSIMD_vector_x_indexed_elem() local
12911 if (!isD) index = (bitH << 1) | bitL; in dis_AdvSIMD_vector_x_indexed_elem()
12912 else if (isD && bitL == 0) index = bitH; in dis_AdvSIMD_vector_x_indexed_elem()
12914 vassert(index < (isD ? 2 : 4)); in dis_AdvSIMD_vector_x_indexed_elem()
12915 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_vector_x_indexed_elem()
12922 assign(res, triop(isD ? Iop_Mul64Fx2 : Iop_Mul32Fx4, in dis_AdvSIMD_vector_x_indexed_elem()
12926 const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s"); in dis_AdvSIMD_vector_x_indexed_elem()
12929 nameQReg128(nn), arr, nameQReg128(mm), isD ? 'd' : 's', index); in dis_AdvSIMD_vector_x_indexed_elem()
13155 Bool isD = opcode == BITS5(0,0,1,0,1); in dis_AdvSIMD_crypto_aes() local
13160 void* helper = isD ? &arm64g_dirtyhelper_AESD in dis_AdvSIMD_crypto_aes()
13162 const HChar* hname = isD ? "arm64g_dirtyhelper_AESD" in dis_AdvSIMD_crypto_aes()
13175 DIP("aes%c %s.16b, %s.16b\n", isD ? 'd' : 'e', in dis_AdvSIMD_crypto_aes()
13449 Bool isD = (ty & 1) == 1; in dis_AdvSIMD_fp_compare() local
13452 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_fp_compare()
13462 ? (IRExpr_Const(isD ? IRConst_F64i(0) : IRConst_F32i(0))) in dis_AdvSIMD_fp_compare()
13464 assign(irRes, binop(isD ? Iop_CmpF64 : Iop_CmpF32, in dis_AdvSIMD_fp_compare()
13514 Bool isD = (ty & 1) == 1; in dis_AdvSIMD_fp_conditional_compare() local
13516 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_fp_conditional_compare()
13522 assign(irRes, binop(isD ? Iop_CmpF64 : Iop_CmpF32, in dis_AdvSIMD_fp_conditional_compare()
13741 Bool isD = (ty & 1) == 1; in dis_AdvSIMD_fp_data_proc_1_source() local
13743 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_fp_data_proc_1_source()
13767 assign(dst, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt, in dis_AdvSIMD_fp_data_proc_1_source()
13904 Bool isD = (ty & 1) == 1; in dis_AdvSIMD_fp_data_proc_3_source() local
13906 IRType ity = isD ? Ity_F64 : Ity_F32; in dis_AdvSIMD_fp_data_proc_3_source()
13958 Bool isD = (ty & 1) == 1; in dis_AdvSIMD_fp_immediate() local
13959 ULong imm = VFPExpandImm(imm8, isD ? 64 : 32); in dis_AdvSIMD_fp_immediate()
13960 if (!isD) { in dis_AdvSIMD_fp_immediate()
13964 putQRegLO(dd, isD ? mkU64(imm) : mkU32(imm & 0xFFFFFFFFULL)); in dis_AdvSIMD_fp_immediate()
13966 nameQRegLO(dd, isD ? Ity_F64 : Ity_F32), imm); in dis_AdvSIMD_fp_immediate()