7434                                /*OUT*/UInt* nLanes, /*OUT*/Bool* zeroUpper,  in getLaneInfo_Q_SZ()  argument
7443       if (nLanes)    *nLanes    = 2;  in getLaneInfo_Q_SZ()
7451       if (nLanes)    *nLanes    = 4;  in getLaneInfo_Q_SZ()
7459       if (nLanes)    *nLanes    = 2;  in getLaneInfo_Q_SZ()
10731       UInt  nLanes = (isQ ? 128 : 64) / lanebits;  in dis_AdvSIMD_shift_by_immediate()  local
10735           nameQReg128(dd), nLanes, laneCh,  in dis_AdvSIMD_shift_by_immediate()
10736           nameQReg128(nn), nLanes, laneCh, shift);  in dis_AdvSIMD_shift_by_immediate()
10774       UInt  nLanes = (isQ ? 128 : 64) / lanebits;  in dis_AdvSIMD_shift_by_immediate()  local
10778           nameQReg128(dd), nLanes, laneCh,  in dis_AdvSIMD_shift_by_immediate()
10779           nameQReg128(nn), nLanes, laneCh, shift);  in dis_AdvSIMD_shift_by_immediate()
10816       UInt  nLanes = (isQ ? 128 : 64) / lanebits;  in dis_AdvSIMD_shift_by_immediate()  local
10818           nameQReg128(dd), nLanes, laneCh,  in dis_AdvSIMD_shift_by_immediate()
10819           nameQReg128(nn), nLanes, laneCh, shift);  in dis_AdvSIMD_shift_by_immediate()
10864       UInt  nLanes = (isQ ? 128 : 64) / lanebits;  in dis_AdvSIMD_shift_by_immediate()  local
10867           nameQReg128(dd), nLanes, laneCh,  in dis_AdvSIMD_shift_by_immediate()
10868           nameQReg128(nn), nLanes, laneCh, shift);  in dis_AdvSIMD_shift_by_immediate()
11091       UInt nLanes = (isQ ? 2 : 1) * (isD ? 1 : 2);  in dis_AdvSIMD_shift_by_immediate()  local
11092       vassert(nLanes == 2 || nLanes == 4);  in dis_AdvSIMD_shift_by_immediate()
11093       for (UInt i = 0; i < nLanes; i++) {  in dis_AdvSIMD_shift_by_immediate()
11137       UInt nLanes = (isQ ? 2 : 1) * (isD ? 1 : 2);  in dis_AdvSIMD_shift_by_immediate()  local
11138       vassert(nLanes == 2 || nLanes == 4);  in dis_AdvSIMD_shift_by_immediate()
11139       for (UInt i = 0; i < nLanes; i++) {  in dis_AdvSIMD_shift_by_immediate()
12560       UInt   nLanes = size == X00 ? 4 : 2;  in dis_AdvSIMD_two_reg_misc()  local
12564       IRTemp src[nLanes];  in dis_AdvSIMD_two_reg_misc()
12565       for (UInt i = 0; i < nLanes; i++) {  in dis_AdvSIMD_two_reg_misc()
12569       for (UInt i = 0; i < nLanes; i++) {  in dis_AdvSIMD_two_reg_misc()
12570          putQRegLane(dd, nLanes * bitQ + i,  in dis_AdvSIMD_two_reg_misc()
12610       UInt   nLanes = size == X00 ? 4 : 2;  in dis_AdvSIMD_two_reg_misc()  local
12613       IRTemp src[nLanes];  in dis_AdvSIMD_two_reg_misc()
12614       for (UInt i = 0; i < nLanes; i++) {  in dis_AdvSIMD_two_reg_misc()
12616          assign(src[i], getQRegLane(nn, nLanes * bitQ + i, srcTy));  in dis_AdvSIMD_two_reg_misc()
12618       for (UInt i = 0; i < nLanes; i++) {  in dis_AdvSIMD_two_reg_misc()
12781          UInt   nLanes = 0;  in dis_AdvSIMD_two_reg_misc()  local
12784          Bool   ok  = getLaneInfo_Q_SZ(&tyI, &tyF, &nLanes, &zeroHI, &arrSpec,  in dis_AdvSIMD_two_reg_misc()
12791          for (i = 0; i < nLanes; i++) {  in dis_AdvSIMD_two_reg_misc()