Lines Matching refs:putQReg128
1382 static void putQReg128 ( UInt qregNo, IRExpr* e ) in putQReg128() function
5469 putQReg128(tt1, mkV128(0x0000)); in dis_ARM64_load_store()
5474 putQReg128(tt2, mkV128(0x0000)); in dis_ARM64_load_store()
5539 putQReg128(tt, mkV128(0x0000)); in dis_ARM64_load_store()
5549 putQReg128(tt, mkV128(0x0000)); in dis_ARM64_load_store()
5559 putQReg128(tt, mkV128(0x0000)); in dis_ARM64_load_store()
5569 putQReg128(tt, mkV128(0x0000)); in dis_ARM64_load_store()
5579 putQReg128(tt, loadLE(Ity_V128, mkexpr(ea))); in dis_ARM64_load_store()
5674 putQReg128(tt, mkV128(0x0000)); in dis_ARM64_load_store()
5725 putQReg128(tt, mkV128(0x0000)); in dis_ARM64_load_store()
5766 putQReg128(tt, mkV128(0x0000)); in dis_ARM64_load_store()
5790 putQReg128(tt, mkV128(0x0000)); in dis_ARM64_load_store()
5972 case 4: putQReg128( (tt+3) % 32, in dis_ARM64_load_store()
5975 case 3: putQReg128( (tt+2) % 32, in dis_ARM64_load_store()
5978 case 2: putQReg128( (tt+1) % 32, in dis_ARM64_load_store()
5981 case 1: putQReg128( (tt+0) % 32, in dis_ARM64_load_store()
6150 case 4: putQReg128( (tt+3) % 32, in dis_ARM64_load_store()
6153 case 3: putQReg128( (tt+2) % 32, in dis_ARM64_load_store()
6156 case 2: putQReg128( (tt+1) % 32, in dis_ARM64_load_store()
6158 putQReg128( (tt+0) % 32, in dis_ARM64_load_store()
6256 putQReg128((tt+3) % 32, math_MAYBE_ZERO_HI64(bitQ, v3)); in dis_ARM64_load_store()
6263 putQReg128((tt+2) % 32, math_MAYBE_ZERO_HI64(bitQ, v2)); in dis_ARM64_load_store()
6270 putQReg128((tt+1) % 32, math_MAYBE_ZERO_HI64(bitQ, v1)); in dis_ARM64_load_store()
6277 putQReg128((tt+0) % 32, math_MAYBE_ZERO_HI64(bitQ, v0)); in dis_ARM64_load_store()
8071 putQReg128(dd, mkexpr(res)); in putLO64andZUorPutHI64()
8074 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(new64))); in putLO64andZUorPutHI64()
8560 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_EXT()
8574 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(res))); in dis_AdvSIMD_EXT()
8632 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_TBL_TBX()
8685 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_ZIP_UZP_TRN()
8708 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_ZIP_UZP_TRN()
8741 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_ZIP_UZP_TRN()
8801 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_across_lanes()
8861 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_across_lanes()
8884 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_across_lanes()
8930 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_copy()
8979 putQReg128(dd, binop(Iop_64HLtoV128, in dis_AdvSIMD_copy()
9310 putQReg128(dd, unop(Iop_ZeroHI64ofV128, res)); in dis_AdvSIMD_modified_immediate()
9313 putQReg128(dd, res); in dis_AdvSIMD_modified_immediate()
9323 putQReg128(dd, immV128); in dis_AdvSIMD_modified_immediate()
9390 putQReg128(dd, binop(Iop_64HLtoV128, mkU64(0), mkexpr(w0))); in dis_AdvSIMD_scalar_copy()
9429 putQReg128(dd, unop(Iop_ZeroHI64ofV128, in dis_AdvSIMD_scalar_pairwise()
9448 putQReg128(dd, unop(opZHI, in dis_AdvSIMD_scalar_pairwise()
9474 putQReg128(dd, unop(opZHI, in dis_AdvSIMD_scalar_pairwise()
9533 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(res))); in dis_AdvSIMD_scalar_shift_by_imm()
9561 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(res))); in dis_AdvSIMD_scalar_shift_by_imm()
9573 putQReg128(dd, unop(Iop_ZeroHI64ofV128, getQReg128(dd))); in dis_AdvSIMD_scalar_shift_by_imm()
9582 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(res))); in dis_AdvSIMD_scalar_shift_by_imm()
9592 putQReg128(dd, in dis_AdvSIMD_scalar_shift_by_imm()
9605 putQReg128(dd, unop(Iop_ZeroHI64ofV128, getQReg128(nn))); in dis_AdvSIMD_scalar_shift_by_imm()
9614 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(res))); in dis_AdvSIMD_scalar_shift_by_imm()
9648 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_scalar_shift_by_imm()
9699 putQReg128(dd, mkexpr(res64in128)); in dis_AdvSIMD_scalar_shift_by_imm()
9845 putQReg128(dd, unop(opZHI, mkexpr(res))); in dis_AdvSIMD_scalar_three_different()
9913 putQReg128(dd, mkexpr(qres)); in dis_AdvSIMD_scalar_three_same()
9932 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(res))); in dis_AdvSIMD_scalar_three_same()
9949 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(res))); in dis_AdvSIMD_scalar_three_same()
9968 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(res))); in dis_AdvSIMD_scalar_three_same()
10003 putQReg128(dd, mkexpr(resSH)); in dis_AdvSIMD_scalar_three_same()
10040 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(res))); in dis_AdvSIMD_scalar_three_same()
10058 putQReg128(dd, in dis_AdvSIMD_scalar_three_same()
10077 putQReg128(dd, mkV128(0x0000)); in dis_AdvSIMD_scalar_three_same()
10092 putQReg128(dd, mkV128(0x0000)); in dis_AdvSIMD_scalar_three_same()
10110 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_three_same()
10124 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_three_same()
10143 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_three_same()
10159 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_three_same()
10211 putQReg128(dd, mkexpr(qres)); in dis_AdvSIMD_scalar_two_reg_misc()
10227 putQReg128(dd, mkexpr(qres)); in dis_AdvSIMD_scalar_two_reg_misc()
10243 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(res))); in dis_AdvSIMD_scalar_two_reg_misc()
10258 putQReg128(dd, unop(Iop_ZeroHI64ofV128, mkexpr(res))); in dis_AdvSIMD_scalar_two_reg_misc()
10265 putQReg128(dd, unop(Iop_ZeroHI64ofV128, in dis_AdvSIMD_scalar_two_reg_misc()
10274 putQReg128(dd, unop(Iop_ZeroHI64ofV128, in dis_AdvSIMD_scalar_two_reg_misc()
10282 putQReg128(dd, unop(Iop_ZeroHI64ofV128, in dis_AdvSIMD_scalar_two_reg_misc()
10323 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_two_reg_misc()
10354 putQReg128(dd, mkexpr(resN)); in dis_AdvSIMD_scalar_two_reg_misc()
10460 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10, in dis_AdvSIMD_scalar_two_reg_misc()
10475 putQReg128(dd, mkV128(0x0000)); in dis_AdvSIMD_scalar_two_reg_misc()
10539 putQReg128(dd, in dis_AdvSIMD_scalar_x_indexed_element()
10568 putQReg128(dd, in dis_AdvSIMD_scalar_x_indexed_element()
10617 putQReg128(dd, unop(opZHI, mkexpr(res))); in dis_AdvSIMD_scalar_x_indexed_element()
10658 putQReg128(dd, unop(opZHI, mkexpr(res))); in dis_AdvSIMD_scalar_x_indexed_element()
10729 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_shift_by_immediate()
10772 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_shift_by_immediate()
10814 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_shift_by_immediate()
10862 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_shift_by_immediate()
10899 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_shift_by_immediate()
11057 putQReg128(dd, res); in dis_AdvSIMD_shift_by_immediate()
11204 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_three_different()
11229 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_three_different()
11295 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_three_different()
11335 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_three_different()
11371 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_three_different()
11421 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_three_different()
11489 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11508 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11542 putQReg128(dd, mkexpr(qres)); in dis_AdvSIMD_three_same()
11564 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11612 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11631 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11650 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11670 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11706 putQReg128(dd, mkexpr(resSH)); in dis_AdvSIMD_three_same()
11728 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t)); in dis_AdvSIMD_three_same()
11750 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t2)); in dis_AdvSIMD_three_same()
11767 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t)); in dis_AdvSIMD_three_same()
11788 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11808 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11828 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11863 putQReg128(dd, res); in dis_AdvSIMD_three_same()
11883 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11912 putQReg128(dd, res); in dis_AdvSIMD_three_same()
11933 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
11958 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t2)); in dis_AdvSIMD_three_same()
11979 putQReg128(dd, mkexpr(t2)); in dis_AdvSIMD_three_same()
11998 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t2)); in dis_AdvSIMD_three_same()
12016 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t1)); in dis_AdvSIMD_three_same()
12034 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t1)); in dis_AdvSIMD_three_same()
12048 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t1)); in dis_AdvSIMD_three_same()
12067 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t1)); in dis_AdvSIMD_three_same()
12094 putQReg128( in dis_AdvSIMD_three_same()
12117 putQReg128( in dis_AdvSIMD_three_same()
12141 putQReg128(dd, mkexpr(t2)); in dis_AdvSIMD_three_same()
12158 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_three_same()
12201 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12215 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12226 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12254 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12288 putQReg128(dd, mkexpr(qres)); in dis_AdvSIMD_two_reg_misc()
12306 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12318 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12329 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12347 putQReg128(dd, mkexpr(qres)); in dis_AdvSIMD_two_reg_misc()
12366 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12384 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12398 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12410 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12421 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12462 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12478 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12550 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_two_reg_misc()
12759 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_two_reg_misc()
12815 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, resV)); in dis_AdvSIMD_two_reg_misc()
12830 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, resV)); in dis_AdvSIMD_two_reg_misc()
12896 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t2)); in dis_AdvSIMD_vector_x_indexed_elem()
12925 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_vector_x_indexed_elem()
12971 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_vector_x_indexed_elem()
13022 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_vector_x_indexed_elem()
13074 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_vector_x_indexed_elem()
13117 putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res)); in dis_AdvSIMD_vector_x_indexed_elem()
13174 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_crypto_aes()
13199 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_crypto_aes()
13292 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_crypto_three_reg_sha()
13388 putQReg128(dd, mkexpr(res)); in dis_AdvSIMD_crypto_two_reg_sha()
13577 putQReg128(dd, mkV128(0x0000)); in dis_AdvSIMD_fp_conditional_select()
13632 putQReg128(dd, mkV128(0x0000)); in dis_AdvSIMD_fp_data_proc_1_source()
13669 putQReg128(dd, mkV128(0x0000)); in dis_AdvSIMD_fp_data_proc_1_source()
13683 putQReg128(dd, mkV128(0x0000)); in dis_AdvSIMD_fp_data_proc_1_source()
13704 putQReg128(dd, mkV128(0x0000)); in dis_AdvSIMD_fp_data_proc_1_source()
13769 putQReg128(dd, mkV128(0x0000)); in dis_AdvSIMD_fp_data_proc_1_source()
13830 putQReg128(dd, mkV128(0)); in dis_AdvSIMD_fp_data_proc_2_source()
13833 putQReg128(dd, unop(mkVecZEROHIxxOFV128(ty+2), in dis_AdvSIMD_fp_data_proc_2_source()
13852 putQReg128(dd, mkV128(0)); in dis_AdvSIMD_fp_data_proc_2_source()
13924 putQReg128(dd, mkV128(0x0000)); in dis_AdvSIMD_fp_data_proc_3_source()
13963 putQReg128(dd, mkV128(0)); in dis_AdvSIMD_fp_immediate()
14082 putQReg128(dd, mkV128(0)); in dis_AdvSIMD_fp_to_from_fixedp_conv()
14264 putQReg128(dd, mkV128(0)); in dis_AdvSIMD_fp_to_from_int_conv()
14308 putQReg128(dd, mkV128(0)); in dis_AdvSIMD_fp_to_from_int_conv()
14313 putQReg128(dd, mkV128(0)); in dis_AdvSIMD_fp_to_from_int_conv()