1541 static void putQRegLane ( UInt qregNo, UInt laneNo, IRExpr* e )  in putQRegLane()  function
6399                   putQRegLane((tt+3) % 32, ix, loadLE(ty, addr));  in dis_ARM64_load_store()
6409                   putQRegLane((tt+2) % 32, ix, loadLE(ty, addr));  in dis_ARM64_load_store()
6419                   putQRegLane((tt+1) % 32, ix, loadLE(ty, addr));  in dis_ARM64_load_store()
6429                   putQRegLane((tt+0) % 32, ix, loadLE(ty, addr));  in dis_ARM64_load_store()
9024          putQRegLane(dd, laneNo, src);  in dis_AdvSIMD_copy()
9170          putQRegLane(dd, ix1, getQRegLane(nn, ix2, ity));  in dis_AdvSIMD_copy()
9740       putQRegLane(dd, 0, mkexpr(res));  in dis_AdvSIMD_scalar_shift_by_imm()
9742          putQRegLane(dd, 1, mkU32(0));  in dis_AdvSIMD_scalar_shift_by_imm()
9744       putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_scalar_shift_by_imm()
9779       putQRegLane(dd, 0, mkexpr(res));  in dis_AdvSIMD_scalar_shift_by_imm()
9781          putQRegLane(dd, 1, mkU32(0));  in dis_AdvSIMD_scalar_shift_by_imm()
9783       putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_scalar_shift_by_imm()
10020       putQRegLane(dd, 0, mkexpr(res));  in dis_AdvSIMD_scalar_three_same()
10021       putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_scalar_three_same()
10374       putQRegLane(dd, 1, mkU32(0));  in dis_AdvSIMD_scalar_two_reg_misc()
10375       putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_scalar_two_reg_misc()
10421       putQRegLane(dd, 0, mkexpr(res)); /* bits 31-0 or 63-0 */  in dis_AdvSIMD_scalar_two_reg_misc()
10423          putQRegLane(dd, 1, mkU32(0)); /* bits 63-32 */  in dis_AdvSIMD_scalar_two_reg_misc()
10425       putQRegLane(dd, 1, mkU64(0));    /* bits 127-64 */  in dis_AdvSIMD_scalar_two_reg_misc()
10443          putQRegLane(dd, 1, mkU32(0)); /* bits 63-32 */  in dis_AdvSIMD_scalar_two_reg_misc()
10445       putQRegLane(dd, 1, mkU64(0));    /* bits 127-64 */  in dis_AdvSIMD_scalar_two_reg_misc()
10476       putQRegLane(dd, 0, mkexpr(res));  in dis_AdvSIMD_scalar_two_reg_misc()
11101          putQRegLane(dd, i, mkexpr(res));  in dis_AdvSIMD_shift_by_immediate()
11104          putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_shift_by_immediate()
11148          putQRegLane(dd, i, mkexpr(res));  in dis_AdvSIMD_shift_by_immediate()
11151          putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_shift_by_immediate()
12570          putQRegLane(dd, nLanes * bitQ + i,  in dis_AdvSIMD_two_reg_misc()
12574          putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_two_reg_misc()
12595          putQRegLane(dd, 2 * bitQ + i,  in dis_AdvSIMD_two_reg_misc()
12599          putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_two_reg_misc()
12619          putQRegLane(dd, i, unop(opCvt, mkexpr(src[i])));  in dis_AdvSIMD_two_reg_misc()
12677             putQRegLane(dd, i, binop(opRND, mkexpr(irrm),  in dis_AdvSIMD_two_reg_misc()
12683             putQRegLane(dd, i, binop(opRND, mkexpr(irrm),  in dis_AdvSIMD_two_reg_misc()
12687             putQRegLane(dd, 1, mkU64(0)); // zero out lanes 2 and 3  in dis_AdvSIMD_two_reg_misc()
12734             putQRegLane(dd, i, binop(cvt, mkU32(irrm),  in dis_AdvSIMD_two_reg_misc()
12740             putQRegLane(dd, i, binop(cvt, mkU32(irrm),  in dis_AdvSIMD_two_reg_misc()
12744             putQRegLane(dd, 1, mkU64(0)); // zero out lanes 2 and 3  in dis_AdvSIMD_two_reg_misc()
12792             putQRegLane(dd, i,  in dis_AdvSIMD_two_reg_misc()
12796             putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_two_reg_misc()