332             AMD64Instr_Alu64R(Aalu_ADD, AMD64RMI_Imm(n),   in add_to_rsp()
340             AMD64Instr_Alu64R(Aalu_SUB, AMD64RMI_Imm(n),   in sub_from_rsp()
351       addInstr( env, AMD64Instr_Push(AMD64RMI_Imm( (UInt)uimm64 )) );  in push_uimm64()
384                    AMD64RMI_Imm(toUInt(e->Iex.Const.con->Ico.U64)),  in iselIntExpr_single_instruction()
731                AMD64Instr_Alu64R(Aalu_ADD, AMD64RMI_Imm(bias), tmp));  in genGuestArrayOffset()
734             AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(7), tmp));  in genGuestArrayOffset()
751    addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(DEFAULT_MXCSR)));  in set_SSE_rounding_default()
794    addInstr(env, AMD64Instr_Alu64R(Aalu_MOV, AMD64RMI_Imm(3), reg));  in set_SSE_rounding_mode()
799                     Aalu_OR, AMD64RMI_Imm(DEFAULT_MXCSR), reg));  in set_SSE_rounding_mode()
826    addInstr(env, AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(3), rrm2));  in set_FPU_rounding_mode()
829                                    AMD64RMI_Imm(DEFAULT_FPUCW), rrm2));  in set_FPU_rounding_mode()
1035                                 Aalu_AND, AMD64RMI_Imm(0xFF), dst));  in iselIntExpr_R_wrk()
1039                                 Aalu_AND, AMD64RMI_Imm(0xFFFF), dst));  in iselIntExpr_R_wrk()
1296                           Aalu_AND, AMD64RMI_Imm(0xFFFF), lo16));  in iselIntExpr_R_wrk()
1311                           Aalu_AND, AMD64RMI_Imm(0xFF), lo8));  in iselIntExpr_R_wrk()
1356          addInstr(env, AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(0x45), dst));  in iselIntExpr_R_wrk()
1387                                             AMD64RMI_Imm(1), dst));  in iselIntExpr_R_wrk()
1479                                             AMD64RMI_Imm(mask), dst));  in iselIntExpr_R_wrk()
1559                                             AMD64RMI_Imm(63), dst));  in iselIntExpr_R_wrk()
1909          addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0x4700),dst));  in iselIntExpr_R_wrk()
2057               return AMD64RMI_Imm(toUInt(e->Iex.Const.con->Ico.U64));  in iselIntExpr_RMI_wrk()
2061             return AMD64RMI_Imm(e->Iex.Const.con->Ico.U32); break;  in iselIntExpr_RMI_wrk()
2063             return AMD64RMI_Imm(0xFFFF & e->Iex.Const.con->Ico.U16); break;  in iselIntExpr_RMI_wrk()
2065             return AMD64RMI_Imm(0xFF & e->Iex.Const.con->Ico.U8); break;  in iselIntExpr_RMI_wrk()
2218       addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(1),dst));  in iselCondCode_wrk()
2229       addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,AMD64RMI_Imm(0),r));  in iselCondCode_wrk()
2284       AMD64RMI* rmi2 = AMD64RMI_Imm(0);  in iselCondCode_wrk()
2310       AMD64RMI* rmi2 = AMD64RMI_Imm(0);  in iselCondCode_wrk()
2337          addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFF),r));  in iselCondCode_wrk()
2357       addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFFFF),r));  in iselCondCode_wrk()
2650       addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));  in iselFltExpr_wrk()
2999       addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));  in iselDblExpr_wrk()
3514          addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));  in iselVecExpr_wrk()
3571                                          AMD64RMI_Imm( ~(UInt)15 ),   in iselVecExpr_wrk()
3623                                          AMD64RMI_Imm( ~(UInt)15 ),   in iselVecExpr_wrk()
3992          addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));  in iselDVecExpr_wrk()
4050                                          AMD64RMI_Imm( ~(UInt)15 ),  in iselDVecExpr_wrk()
4128                                          AMD64RMI_Imm( ~(UInt)15 ),  in iselDVecExpr_wrk()