734             AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(7), tmp));  in genGuestArrayOffset()
795    addInstr(env, AMD64Instr_Alu64R(Aalu_AND,  in set_SSE_rounding_mode()
826    addInstr(env, AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(3), rrm2));  in set_FPU_rounding_mode()
988             aluOp = Aalu_AND; break;  in iselIntExpr_R_wrk()
1035                                 Aalu_AND, AMD64RMI_Imm(0xFF), dst));  in iselIntExpr_R_wrk()
1039                                 Aalu_AND, AMD64RMI_Imm(0xFFFF), dst));  in iselIntExpr_R_wrk()
1296                           Aalu_AND, AMD64RMI_Imm(0xFFFF), lo16));  in iselIntExpr_R_wrk()
1311                           Aalu_AND, AMD64RMI_Imm(0xFF), lo8));  in iselIntExpr_R_wrk()
1356          addInstr(env, AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(0x45), dst));  in iselIntExpr_R_wrk()
1386             addInstr(env, AMD64Instr_Alu64R(Aalu_AND,  in iselIntExpr_R_wrk()
1429             case Iop_And32: aluOp = Aalu_AND; break;  in iselIntExpr_R_wrk()
1478             addInstr(env, AMD64Instr_Alu64R(Aalu_AND,  in iselIntExpr_R_wrk()
1909          addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0x4700),dst));  in iselIntExpr_R_wrk()
2218       addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(1),dst));  in iselCondCode_wrk()
2337          addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFF),r));  in iselCondCode_wrk()
2357       addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFFFF),r));  in iselCondCode_wrk()
3570          addInstr(env, AMD64Instr_Alu64R(Aalu_AND,  in iselVecExpr_wrk()
3622          addInstr(env, AMD64Instr_Alu64R(Aalu_AND,  in iselVecExpr_wrk()
4049          addInstr(env, AMD64Instr_Alu64R(Aalu_AND,  in iselDVecExpr_wrk()
4127          addInstr(env, AMD64Instr_Alu64R(Aalu_AND,  in iselDVecExpr_wrk()