Lines Matching refs:Aalu_OR
799 Aalu_OR, AMD64RMI_Imm(DEFAULT_MXCSR), reg)); in set_SSE_rounding_mode()
828 addInstr(env, AMD64Instr_Alu64R(Aalu_OR, in set_FPU_rounding_mode()
990 aluOp = Aalu_OR; break; in iselIntExpr_R_wrk()
1269 addInstr(env, AMD64Instr_Alu64R(Aalu_OR, AMD64RMI_Reg(rdx), dst)); in iselIntExpr_R_wrk()
1283 Aalu_OR, AMD64RMI_Reg(lo32), hi32)); in iselIntExpr_R_wrk()
1298 Aalu_OR, AMD64RMI_Reg(lo16), hi16)); in iselIntExpr_R_wrk()
1313 Aalu_OR, AMD64RMI_Reg(lo8), hi8)); in iselIntExpr_R_wrk()
1430 case Iop_Or32: aluOp = Aalu_OR; break; in iselIntExpr_R_wrk()
1570 addInstr(env, AMD64Instr_Alu64R(Aalu_OR, in iselIntExpr_R_wrk()
1584 addInstr(env, AMD64Instr_Alu64R(Aalu_OR, in iselIntExpr_R_wrk()
1598 addInstr(env, AMD64Instr_Alu64R(Aalu_OR, AMD64RMI_Reg(src), dst)); in iselIntExpr_R_wrk()
2301 addInstr(env, AMD64Instr_Alu64R(Aalu_OR,rmi1,tmp)); in iselCondCode_wrk()