Lines Matching refs:VBinS
1136 i->ARM64in.VBinS.op = op; in ARM64Instr_VBinS()
1137 i->ARM64in.VBinS.dst = dst; in ARM64Instr_VBinS()
1138 i->ARM64in.VBinS.argL = argL; in ARM64Instr_VBinS()
1139 i->ARM64in.VBinS.argR = argR; in ARM64Instr_VBinS()
1728 vex_printf("f%s ", showARM64FpBinOp(i->ARM64in.VBinS.op)); in ppARM64Instr()
1729 ppHRegARM64asSreg(i->ARM64in.VBinS.dst); in ppARM64Instr()
1731 ppHRegARM64asSreg(i->ARM64in.VBinS.argL); in ppARM64Instr()
1733 ppHRegARM64asSreg(i->ARM64in.VBinS.argR); in ppARM64Instr()
2155 addHRegUse(u, HRmWrite, i->ARM64in.VBinS.dst); in getRegUsage_ARM64Instr()
2156 addHRegUse(u, HRmRead, i->ARM64in.VBinS.argL); in getRegUsage_ARM64Instr()
2157 addHRegUse(u, HRmRead, i->ARM64in.VBinS.argR); in getRegUsage_ARM64Instr()
2404 i->ARM64in.VBinS.dst = lookupHRegRemap(m, i->ARM64in.VBinS.dst); in mapRegs_ARM64Instr()
2405 i->ARM64in.VBinS.argL = lookupHRegRemap(m, i->ARM64in.VBinS.argL); in mapRegs_ARM64Instr()
2406 i->ARM64in.VBinS.argR = lookupHRegRemap(m, i->ARM64in.VBinS.argR); in mapRegs_ARM64Instr()
4209 UInt sD = dregEnc(i->ARM64in.VBinS.dst); in emit_ARM64Instr()
4210 UInt sN = dregEnc(i->ARM64in.VBinS.argL); in emit_ARM64Instr()
4211 UInt sM = dregEnc(i->ARM64in.VBinS.argR); in emit_ARM64Instr()
4213 switch (i->ARM64in.VBinS.op) { in emit_ARM64Instr()