Lines Matching refs:VLdStD
1252 i->ARMin.VLdStD.isLoad = isLoad; in ARMInstr_VLdStD()
1253 i->ARMin.VLdStD.dD = dD; in ARMInstr_VLdStD()
1254 i->ARMin.VLdStD.amode = am; in ARMInstr_VLdStD()
1755 if (i->ARMin.VLdStD.isLoad) { in ppARMInstr()
1757 ppHRegARM(i->ARMin.VLdStD.dD); in ppARMInstr()
1759 ppARMAModeV(i->ARMin.VLdStD.amode); in ppARMInstr()
1762 ppARMAModeV(i->ARMin.VLdStD.amode); in ppARMInstr()
1764 ppHRegARM(i->ARMin.VLdStD.dD); in ppARMInstr()
2225 addRegUsage_ARMAModeV(u, i->ARMin.VLdStD.amode); in getRegUsage_ARMInstr()
2226 if (i->ARMin.VLdStD.isLoad) { in getRegUsage_ARMInstr()
2227 addHRegUse(u, HRmWrite, i->ARMin.VLdStD.dD); in getRegUsage_ARMInstr()
2229 addHRegUse(u, HRmRead, i->ARMin.VLdStD.dD); in getRegUsage_ARMInstr()
2476 i->ARMin.VLdStD.dD = lookupHRegRemap(m, i->ARMin.VLdStD.dD); in mapRegs_ARMInstr()
2477 mapRegs_ARMAModeV(m, i->ARMin.VLdStD.amode); in mapRegs_ARMInstr()
3618 UInt dD = dregEnc(i->ARMin.VLdStD.dD); in emit_ARMInstr()
3619 UInt rN = iregEnc(i->ARMin.VLdStD.amode->reg); in emit_ARMInstr()
3620 Int simm11 = i->ARMin.VLdStD.amode->simm11; in emit_ARMInstr()
3623 UInt bL = i->ARMin.VLdStD.isLoad ? 1 : 0; in emit_ARMInstr()